Hi Chen,
On 8/7/2026 9:12 am, Chen Huei Lok wrote:
DDR retention lets N5X skip a full DDR re-calibration across a warm reset by reusing previously calibrated PHY data, which significantly shortens warm reboot time. To do this the SPL must, early in boot and before DRAM is usable, locate a known-good backup of the calibration data, verify it, and replay it into the DDR PHY before handoff. Enable the configs that this restore path depends on: - CONFIG_FS_LOADER / CONFIG_SPL_FS_LOADER: the generic firmware loader is used by the DDR driver (request_firmware_into_buf()) to pull the backup calibration header and data from the QSPI/NAND RAW partition into the OCRAM scratch buffer (SOC64_OCRAM_PHY_BACKUP_BASE). The loader device is resolved through the "firmware-loader" phandle on the DDR node, falling back to /chosen. SPL_FS_LOADER is required because the restore runs in SPL, before DRAM is available. - CONFIG_SHA384: the calibration backup is bound to the current DDR configuration with a SHA-384 digest (sha384_csum_wd() over the DDR handoff image and the mem-clk table). On store the digest is written into the backup header; on restore it is recomputed and compared (is_ddrconfig_hash_match()), so a backup that no longer matches the running DDR / mem-clk configuration is rejected. Enabling SHA384 selects the SHA-512 implementation it is built on, so CONFIG_SHA512_ALGO does not need to be listed explicitly. - CONFIG_SPL_ENV_SUPPORT: the firmware loader reads its storage selection from the environment (storage_interface, fw_dev_part, ...), so the environment must be accessible in SPL for the loader to bind the backing flash device. Init order and failure modes: the restore is best-effort and fully guarded. The buffer load is bounds-checked against the HPS handoff region (SOC64_HANDOFF_BASE) to prevent overflow, the header magic must match, a CRC32 over the data must match, and finally the SHA-384 config hash must match. If any check fails (missing loader, read error, bad magic, CRC or hash mismatch) the backup is discarded and DDR falls back to a normal full calibration, so an invalid or stale backup never corrupts bring-up. These symbols are enabled only after the fs_loader RAW-partition support and the N5X self-refresh / retention restore code that consume them, so the series stays bisectable. The defconfig is kept in canonical savedefconfig order; CONFIG_SPL_CRC32 is now selected implicitly by the options enabled here and is therefore dropped from the explicit list. Signed-off-by: Tien Fong Chee <[email protected]> Signed-off-by: Chen Huei Lok <[email protected]> --- configs/socfpga_n5x_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 8f4723398df..4683726208e 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -42,6 +42,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y +CONFIG_SPL_ENV_SUPPORT=y
Confirm SPL_ENV_SUPPORT is required for RAW retention path? [...] Best regards, Tien Fong
