get_cpu_rev() reads the Cortex-A9 SCU configuration register even on Cortex-A7 based i.MX6UL, i.MX6ULL and i.MX6ULZ SoCs, where the address is reserved.
Read the SCU configuration only for the raw MX6DL and MX6Q IDs, which need the core count to distinguish Solo, DualLite, Dual, Quad and Plus variants. Other SoCs skip the access. Signed-off-by: Bin Meng <[email protected]> --- arch/arm/mach-imx/mx6/soc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 02df86156d4..824e8ca6d8a 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -71,15 +71,17 @@ u32 get_nr_cpus(void) u32 get_cpu_rev(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; u32 reg = readl(&anatop->digprog_sololite); u32 type = ((reg >> 16) & 0xff); u32 major, cfg = 0; if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); - struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; - cfg = readl(&scu->config) & 3; type = ((reg >> 16) & 0xff); + if (type == MXC_CPU_MX6DL || type == MXC_CPU_MX6Q) + cfg = readl(&scu->config) & 3; + if (type == MXC_CPU_MX6DL) { if (!cfg) type = MXC_CPU_MX6SOLO; --- base-commit: 8d7bc8add17bbc69a58dfe0002eea039dd2dc1bc branch: imx6ul -- 2.53.0
