Hi Jonas,
On 8/4/26 2:26 AM, Jonas Karlman wrote:
The ACLK_BUS clock is initialized to 150 MHz in SPL on RK3568.
Ensure clock driver is always probed after bind for SPL builds to
initialize core PLLs and clocks in SPL phase on RK3568.
You explain what this does but not why? What are the symptoms? Why is
this the proper way to fix the issue?
Based on Heiko's message, I'm guessing the issue is that we need
something to setup clocks that are only accessible from the secure world
and SPL happens to be running in it, but not proper (nor is the kernel).
Hence why Heiko needs this in order for the "DSI panel to work again"
(I'm assuming in the kernel hence why any fix in any driver/device tree
to enable the clock is not gonna help with the issue).
This seems to be a bandaid patch instead of fixing the issue (that is,
the kernel should enable/control this clock through some mechanisms,
e.g. by interacting with TF-A through SCMI).
Heiko also said "my DSI panel work again" which implies it worked at
some point and got broken since, so it'd be nice to know what broke it
so we can have all the clues necessary to fix the issue in the long
term. Considering we broke something, I won't resist too much on this
patch even though based on the above guesses we're fixing a kernel bug
in U-Boot.
Can you please confirm my guess or clarify?
Cheers,
Quentin
Signed-off-by: Jonas Karlman <[email protected]>
---
drivers/clk/rockchip/clk_rk3568.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3568.c
b/drivers/clk/rockchip/clk_rk3568.c
index 9f3e9322161e..5a05f1b4de00 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -2934,6 +2934,10 @@ static int rk3568_clk_bind(struct udevice *dev)
struct udevice *sys_child;
struct sysreset_reg *priv;
+ /* Ensure clocks are initialized after bind in SPL build */
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
/* The reset driver does not have a device node, so bind it here */
ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
&sys_child);
