On Tue, 22 Sep 2026 22:16:40 +0800, kongchen wrote:
> DMA_MODE.SWR resets the whole MAC core and only self-clears once all
> of the MAC's clock domains are running. On SoCs where the RGMII RX
> clock is sourced by the PHY (e.g. Rockchip RK3568), the RX clock
> domain stays dead until the PHY has been brought up: PHYs like the
> Maxio MAE0621A need a vendor-specific init sequence (crystal clock
> mode plus analog tuning) before they start outputting RXC at all.
>
> [...]
Applied to u-boot-net branch for-next, thanks!
[1/2] net: dwc_eth_qos: bring PHY up before triggering DMA soft reset
commit: 1a5da2d56fbd9027ceb7977599d5d793ffd1eb7f
[2/2] net: phy: add support for Maxio MAE0621A Ethernet PHYs
commit: 8f3113936ba37844cf39574ea7914e3fbc723172
Best regards,
--
Jerome Forissier <[email protected]>
