The P3041DS development system is unmaintained and lacks active community testing. Drop its target and device tree.
Signed-off-by: Bradley Morgan <[email protected]> --- arch/powerpc/cpu/mpc85xx/Kconfig | 9 -- arch/powerpc/dts/Makefile | 1 - arch/powerpc/dts/p3041.dtsi | 149 --------------------------- arch/powerpc/dts/p3041ds.dts | 158 ----------------------------- arch/powerpc/dts/p3041si-post.dtsi | 43 -------- board/nxp/common/Makefile | 2 - 6 files changed, 362 deletions(-) delete mode 100644 arch/powerpc/dts/p3041.dtsi delete mode 100644 arch/powerpc/dts/p3041ds.dts delete mode 100644 arch/powerpc/dts/p3041si-post.dtsi diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 7e885014ebe..65081b5bd63 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -87,15 +87,6 @@ config TARGET_SOCRATES select ARCH_MPC8544 select BINMAN -config TARGET_P3041DS - bool "Support P3041DS" - select PHYS_64BIT - select ARCH_P3041 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select FSL_NGPIXIS - imply SATA - imply PANIC_HANG - config TARGET_P4080DS bool "Support P4080DS" select PHYS_64BIT diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index e44d49cabdf..c603369e7cc 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -11,7 +11,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb -dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb dtb-$(CONFIG_TARGET_SOCRATES) += socrates.dtb diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi deleted file mode 100644 index e34117b65a0..00000000000 --- a/arch/powerpc/dts/p3041.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * P3041 Silicon/SoC Device Tree Source (pre include) - * - * Copyright 2010 - 2015 Freescale Semiconductor Inc. - * Copyright 2019-2020 NXP - */ - -/dts-v1/; - -/include/ "e500mc_power_isa.dtsi" - -/ { - compatible = "fsl,P3041"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mpic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: PowerPC,e500mc@0 { - device_type = "cpu"; - reg = <0>; - fsl,portid-mapping = <0x80000000>; - }; - cpu1: PowerPC,e500mc@1 { - device_type = "cpu"; - reg = <1>; - fsl,portid-mapping = <0x40000000>; - }; - cpu2: PowerPC,e500mc@2 { - device_type = "cpu"; - reg = <2>; - fsl,portid-mapping = <0x20000000>; - }; - cpu3: PowerPC,e500mc@3 { - device_type = "cpu"; - reg = <3>; - fsl,portid-mapping = <0x10000000>; - }; - }; - - soc: soc@ffe000000 { - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - compatible = "simple-bus"; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <4>; - reg = <0x40000 0x40000>; - compatible = "fsl,mpic", "chrp,open-pic"; - device_type = "open-pic"; - clock-frequency = <0x0>; - }; - - espi0: spi@110000 { - compatible = "fsl,mpc8536-espi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x110000 0x1000>; - fsl,espi-num-chipselects = <4>; - status = "disabled"; - }; - - usb0: usb@fe210000 { - compatible = "fsl-usb2-mph"; - reg = <0x210000 0x1000>; - phy_type = "utmi"; - }; - - usb1: usb@fe211000 { - compatible = "fsl-usb2-dr"; - reg = <0x211000 0x1000>; - phy_type = "utmi"; - }; - - sata: sata@220000 { - compatible = "fsl,pq-sata-v2"; - reg = <0x220000 0x1000>; - interrupts = <68 0x2 0 0>; - sata-offset = <0x1000>; - sata-number = <2>; - sata-fpdma = <0>; - }; - - esdhc: esdhc@114000 { - compatible = "fsl,esdhc"; - reg = <0x114000 0x1000>; - clock-frequency = <0>; - }; - /include/ "qoriq-i2c-0.dtsi" - /include/ "qoriq-i2c-1.dtsi" - }; - - pcie@ffe200000 { - compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ - law_trgt_if = <0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe201000 { - compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ - law_trgt_if = <1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe202000 { - compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ - law_trgt_if = <2>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe203000 { - compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */ - law_trgt_if = <3>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; -}; diff --git a/arch/powerpc/dts/p3041ds.dts b/arch/powerpc/dts/p3041ds.dts deleted file mode 100644 index 069dae3b85b..00000000000 --- a/arch/powerpc/dts/p3041ds.dts +++ /dev/null @@ -1,158 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * P3041DS Device Tree Source - * - * Copyright 2010 - 2015 Freescale Semiconductor Inc. - * Copyright 2019-2020 NXP - */ - -/include/ "p3041.dtsi" - -/ { - model = "fsl,P3041DS"; - compatible = "fsl,P3041DS"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mpic>; - - aliases{ - phy_rgmii_0 = &phy_rgmii_0; - phy_rgmii_1 = &phy_rgmii_1; - phy_sgmii_1c = &phy_sgmii_1c; - phy_sgmii_1d = &phy_sgmii_1d; - phy_sgmii_1e = &phy_sgmii_1e; - phy_sgmii_1f = &phy_sgmii_1f; - phy_xgmii_1 = &phy_xgmii_1; - phy_xgmii_2 = &phy_xgmii_2; - emi1_rgmii = &hydra_mdio_rgmii; - emi1_sgmii = &hydra_mdio_sgmii; - emi2_xgmii = &hydra_mdio_xgmii; - spi0 = &espi0; - }; - - soc: soc@ffe000000 { - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - fman@400000{ - ethernet@e0000 { - phy-handle = <&phy_sgmii_1c>; - phy-connection-type = "sgmii"; - }; - - ethernet@e2000 { - phy-handle = <&phy_sgmii_1d>; - phy-connection-type = "sgmii"; - }; - - ethernet@e4000 { - phy-handle = <&phy_sgmii_1e>; - phy-connection-type = "sgmii"; - }; - - ethernet@e6000 { - phy-handle = <&phy_sgmii_1f>; - phy-connection-type = "sgmii"; - }; - - ethernet@e8000 { - phy-handle = <&phy_rgmii_1>; - phy-connection-type = "rgmii"; - }; - - ethernet@f0000 { - phy-handle = <&phy_xgmii_1>; - phy-connection-type = "xgmii"; - }; - - hydra_mdio_xgmii: mdio@f1000 { - status = "disabled"; - - phy_xgmii_1: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0x4>; - }; - - phy_xgmii_2: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0x0>; - }; - }; - }; - }; - - lbc: localbus@ffe124000 { - reg = <0xf 0xfe124000 0 0x1000>; - ranges = <0 0 0xf 0xe8000000 0x08000000 - 2 0 0xf 0xffa00000 0x00040000 - 3 0 0xf 0xffdf0000 0x00008000>; - - board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis"; - reg = <3 0 0x30>; - ranges = <0 3 0 0x30>; - - mdio-mux-emi1 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "mdio-mux-mmioreg", "mdio-mux"; - mdio-parent-bus = <&mdio0>; - reg = <9 1>; - mux-mask = <0x78>; - - hydra_mdio_rgmii: rgmii-mdio@8 { - #address-cells = <1>; - #size-cells = <0>; - reg = <8>; - status = "disabled"; - - phy_rgmii_0: ethernet-phy@0 { - reg = <0x0>; - }; - - phy_rgmii_1: ethernet-phy@1 { - reg = <0x1>; - }; - }; - - hydra_mdio_sgmii: sgmii-mdio@28 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x28>; - status = "disabled"; - - phy_sgmii_1c: ethernet-phy@1c { - reg = <0x1c>; - }; - - phy_sgmii_1d: ethernet-phy@1d { - reg = <0x1d>; - }; - - phy_sgmii_1e: ethernet-phy@1e { - reg = <0x1e>; - }; - - phy_sgmii_1f: ethernet-phy@1f { - reg = <0x1f>; - }; - }; - }; - }; - }; -}; - -&espi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - /* input clock */ - spi-max-frequency = <10000000>; - }; -}; - -/include/ "p3041si-post.dtsi" diff --git a/arch/powerpc/dts/p3041si-post.dtsi b/arch/powerpc/dts/p3041si-post.dtsi deleted file mode 100644 index a3e8088d25b..00000000000 --- a/arch/powerpc/dts/p3041si-post.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * P3041 Silicon/SoC Device Tree Source (post include) - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2020 NXP - * - */ - -&soc { - -/include/ "qoriq-clockgen1.dtsi" -/include/ "qoriq-gpio-0.dtsi" -/include/ "qoriq-sec4.2-0.dtsi" - -/* include used FMan blocks */ -/include/ "qoriq-fman-0.dtsi" -/include/ "qoriq-fman-0-1g-0.dtsi" -/include/ "qoriq-fman-0-1g-1.dtsi" -/include/ "qoriq-fman-0-1g-2.dtsi" -/include/ "qoriq-fman-0-1g-3.dtsi" -/include/ "qoriq-fman-0-1g-4.dtsi" -/include/ "qoriq-fman-0-10g-0.dtsi" - fman@400000 { - enet0: ethernet@e0000 { - }; - - enet1: ethernet@e2000 { - }; - - enet2: ethernet@e4000 { - }; - - enet3: ethernet@e6000 { - }; - - enet4: ethernet@e8000 { - }; - - enet5: ethernet@f0000 { - }; - }; -}; diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile index 46e43a4e45a..ba1aa084aa4 100644 --- a/board/nxp/common/Makefile +++ b/board/nxp/common/Makefile @@ -49,7 +49,6 @@ obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o endif -obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y) @@ -67,7 +66,6 @@ obj-$(CONFIG_EMC2305) += emc2305.o # deal with common files for P-series corenet based devices obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ -obj-$(CONFIG_TARGET_P3041DS) += p_corenet/ obj-$(CONFIG_TARGET_P4080DS) += p_corenet/ obj-$(CONFIG_TARGET_P5040DS) += p_corenet/ -- 2.47.3
