Re: [PATCH] fpga: versalpl: move PDI load operation into firmware helper

[Michal Simek]

On 9/21/26 20:58, Akshay Belsare wrote:

versal_load() calls xilinx_pm_request() directly for the PDI load
IOCTL, including Versal Gen 2-specific buffer address handling.

Move it into zynqmp_pm_fpga_load() in firmware-zynqmp.c. The Gen 2
buffer ordering now uses IS_ENABLED(CONFIG_ARCH_VERSAL2) instead of a
runtime desc->family check, which is equivalent since U-Boot builds
one board per image.

Also add a weak no-op default in versalpl.c so the driver still links
when CONFIG_ZYNQMP_FIRMWARE is disabled.

Signed-off-by: Akshay Belsare <akshay.bels...@amd.com>
---
  drivers/firmware/firmware-zynqmp.c | 15 +++++++++++++++
  drivers/fpga/versalpl.c            | 20 +++++++-------------
  include/zynqmp_firmware.h          |  1 +
  3 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/drivers/firmware/firmware-zynqmp.c 
b/drivers/firmware/firmware-zynqmp.c
index fae66ccb3d8..ddfdb0cb195 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -14,6 +14,7 @@
  #include <dm/device_compat.h>
  #include <dm/lists.h>
  #include <log.h>
+#include <versalpl.h>
  #include <zynqmp_firmware.h>
  #include <asm/cache.h>
  #include <asm/ptrace.h>
@@ -175,6 +176,20 @@ unsigned int zynqmp_firmware_version(void)
        return pm_api_version;
  };

+int zynqmp_pm_fpga_load(u64 address)

+{
+       u32 buf_lo = lower_32_bits(address);
+       u32 buf_hi = upper_32_bits(address);
+       u32 ret_payload[PAYLOAD_ARG_CNT];
+
+       if (IS_ENABLED(CONFIG_ARCH_VERSAL2))
+               return xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE,
+                                        buf_hi, buf_lo, 0, 0, 0, ret_payload);
+
+       return xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE,
+                                buf_lo, buf_hi, 0, 0, 0, ret_payload);
+}
+
  #if defined(CONFIG_ARCH_VERSAL2)
  /*
   * Poll the M-PHY TX/RX config-ready status until it settles or @timeout_us
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
index 3cb56cc0dc9..29d2a389fd9 100644
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@@ -10,6 +10,7 @@
  #include <versalpl.h>
  #include <zynqmp_firmware.h>
  #include <asm/cache.h>
+#include <linux/errno.h>

static ulong versal_align_dma_buffer(ulong *buf, u32 len)

  {
@@ -24,30 +25,23 @@ static ulong versal_align_dma_buffer(ulong *buf, u32 len)
        return (ulong)buf;
  }

+__weak int zynqmp_pm_fpga_load(u64 address)

+{
+       return -ENOSYS;
+}
+
  static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
                       bitstream_type bstype, int flags)
  {
        ulong bin_buf;
        int ret;
-       u32 buf_lo, buf_hi;
-       u32 ret_payload[PAYLOAD_ARG_CNT];

bin_buf = versal_align_dma_buffer((ulong *)buf, bsize); debug("%s called!\n", __func__);

        flush_dcache_range(bin_buf, bin_buf + bsize);

- buf_lo = lower_32_bits(bin_buf);

-       buf_hi = upper_32_bits(bin_buf);
-
-       if (desc->family == xilinx_versal2) {
-               ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, 
buf_hi,
-                                       buf_lo, 0, 0, 0, ret_payload);
-       } else {
-               ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, 
buf_lo,
-                                       buf_hi, 0, 0, 0, ret_payload);
-       }
-
+       ret = zynqmp_pm_fpga_load(bin_buf);
        if (ret)
                printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);

diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h

index f753a67ac27..e0759359846 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -467,6 +467,7 @@ int zynqmp_pm_feature(const u32 api_id);
  u32 zynqmp_pm_get_bootmode_reg(void);
  u32 zynqmp_pm_get_pmc_multi_boot_reg(void);
  u32 zynqmp_pm_get_pmc_global_pggs_reg(u32 reg_addr);
+int zynqmp_pm_fpga_load(u64 address);

/* Type of Config Object */

  #define PM_CONFIG_OBJECT_TYPE_BASE    0x1U

Applied.
M