Some boards probe their DDR configuration by calling ddr_init() several times with different timings until one of them works, e.g. the Kontron SL i.MX8MM and OSM-S i.MX8MP. This only works reliably as long as the previous training run failed. If it succeeded, the DDRMIX is left in a state that the power up procedure in ddr_init() doesn't expect: the DDRC is in normal operating mode and the PHY keeps the results of the last training run. The next ddr_init() then reports success, but the DRAM is not functional. Depending on the SoC, accesses either fail or freeze the system.
The OSM-S i.MX8MP board code contains a workaround for this that was found by trial and error: a short additional size check before the second ddr_init() call. It doesn't fix the root cause, and other boards run into the same problem as soon as their probing tries a configuration that trains successfully on the wrong DDR. This happens for example when adding a 4GB single rank configuration to the SL i.MX8MM probing, which also trains successfully on the 1GB variant. This series fixes the issue by bringing the DDRMIX back to its power-on state before ddr_init() is repeated. The DRAM traffic is stopped, the DDRMIX resets are asserted and the DDRMIX power domain is power cycled through the GPC. Asserting the resets alone is not sufficient. The power down sequence follows dram_enter_retention() in TF-A. Patch 1 fixes the GPC registers used by the existing power up procedure on i.MX8MP, which uses a different GPC layout than the other i.MX8M SoCs. This is a prerequisite for powering up the DDRMIX again after it has been turned off. Patch 2 adds the DDRMIX reset for i.MX8MM, i.MX8MN and i.MX8MP. The i.MX8MQ has a second DDR domain and is left unchanged. Patch 3 removes the now obsolete workaround from the OSM-S i.MX8MP board code. Tested on a Kontron OSM-S i.MX8MP with 4GB LPDDR4, which first trains the 8GB configuration successfully and then repeats ddr_init() with the 4GB configuration. Without this series and without the workaround the board freezes, with this series the 4GB are detected and pass a memory test above the 4GB boundary. Also tested on a Kontron SL i.MX8MM with 1GB LPDDR4 to make sure the DDR probing there keeps working. Signed-off-by: Frieder Schrempf <[email protected]> --- Frieder Schrempf (3): ddr: imx: Use the correct GPC registers for the i.MX8MP DDRMIX ddr: imx: Recreate the power-on state before repeating ddr_init() imx: kontron-osm-s-mx8mp: Remove DDR reinit workaround arch/arm/include/asm/arch-imx8m/imx-regs.h | 10 ++ board/kontron/osm-s-mx8mp/spl.c | 14 --- drivers/ddr/imx/imx8m/ddr_init.c | 189 ++++++++++++++++++++++++++++- 3 files changed, 197 insertions(+), 16 deletions(-) --- base-commit: 65a7532545336e4b73e049a69436e255da7df961 change-id: 20261015-feature-main-imx8m-ddr-reinit-8d145fef8c5d Best regards, -- Frieder Schrempf <[email protected]>
