[PATCH v3 2/5] clk: rockchip: rk3568: Always initialize clocks in SPL

[Jonas Karlman]

The RK3568 clock driver initializes ACLK_BUS to 150 MHz when probed in
SPL. However, the driver is only probed on demand, so this
initialization is skipped when no SPL consumer requests a clock, e.g.
when booting from RAM/USB.

Prior to the commit c6bba31dbdd4 ("rockchip: spl-boot-order: Defer probe
of boot device") all boot devices where typically probed, with a side
effect that clock driver likely also where probed, prior to the
boot_from_devices() call.

Flag the clock drivers to be probed after bind in SPL to help ensure a
deterministic probe and clock initialization behavior prior to booting
from devices.

Signed-off-by: Jonas Karlman <jo...@kwiboo.se>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v3:
- Also add probe-after-bind to the pmucru driver for consistency. The
  PPLL default rate is 24 MHz and is changed to 200 MHz in probe(), this
  also happens in proper so probe() in SPL is strictly not needed.

Changes in v2:
- Update commit message
- Collect r-b tag
---
 drivers/clk/rockchip/clk_rk3568.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3568.c 
b/drivers/clk/rockchip/clk_rk3568.c
index ce17d42ea0f0..c3973215c37e 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -494,14 +494,19 @@ static int rk3568_pmuclk_ofdata_to_platdata(struct 
udevice *dev)
 
 static int rk3568_pmuclk_bind(struct udevice *dev)
 {
-#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
-       int ret = 0;
+       int ret;
+
+       /* Ensure clocks are initialized after bind in SPL build */
+       if (IS_ENABLED(CONFIG_SPL_BUILD))
+               dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+       if (!CONFIG_IS_ENABLED(RESET_ROCKCHIP))
+               return 0;
 
        ret = offsetof(struct rk3568_pmucru, pmu_softrst_con[0]);
        ret = rockchip_reset_bind(dev, ret, 1);
        if (ret)
                debug("Warning: pmucru software reset driver bind failed\n");
-#endif
 
        return 0;
 }
@@ -2936,6 +2941,10 @@ static int rk3568_clk_bind(struct udevice *dev)
        struct udevice *sys_child;
        struct sysreset_reg *priv;
 
+       /* Ensure clocks are initialized after bind in SPL build */
+       if (IS_ENABLED(CONFIG_SPL_BUILD))
+               dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
        /* The reset driver does not have a device node, so bind it here */
        ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
                                 &sys_child);
-- 
2.55.0