I'm working on a GENI SPI driver for QUPv3 platforms and the SPI controller on SDM845 is QUP0 SE4. U-Boot can currently only describe the UART9 pins on this SoC and its clock driver cannot set the SE4 rate.
The mux value of the SE4 pins differs per pin which the per-function pinctrl table cannot express. Therefore the first patch makes the lookup per pin. The second patch lets the clock driver set the SE4 SPI clock rate. Signed-off-by: Petr Hodina <[email protected]> --- Petr Hodina (2): pinctrl: qcom: sdm845: select the mux value per pin clk: qcom: sdm845: add GCC_QUPV3_WRAP0_S4_CLK case drivers/clk/qcom/clock-sdm845.c | 10 ++++++-- drivers/pinctrl/qcom/pinctrl-sdm845.c | 45 +++++++++++++++++++++++++++++++---- 2 files changed, 48 insertions(+), 7 deletions(-) --- base-commit: 1bcb2fe324180d0a8cfbdb0511737eba1d5b8550 change-id: 20261016-b4-sdm845-qupv3-s4-18edc95821d0 Best regards, -- Petr Hodina <[email protected]>
