The controller initialization only handles the dual rank configuration and fails with -EINVAL when the firmware describes a single rank, as it is the case for the BeagleV-Ahead.
Select the rank configuration in MSTR and the matching address mapping in ADDRMAP0 from the number of ranks described by the firmware, with the values used for 64-bit LPDDR4X by the vendor DDR initialization code. Signed-off-by: Thomas Perrot <[email protected]> --- drivers/ram/thead/th1520_ddr.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/ram/thead/th1520_ddr.c b/drivers/ram/thead/th1520_ddr.c index bb4736b02362..6e88ec0256c5 100644 --- a/drivers/ram/thead/th1520_ddr.c +++ b/drivers/ram/thead/th1520_ddr.c @@ -309,10 +309,16 @@ static int th1520_ddr_ctrl_init(void __iomem *ctrlreg, struct th1520_ddr_fw *fw) if (ret) return ret; - if (fw->ranknum == 2) + switch (fw->ranknum) { + case 1: + writel(0x01080020, ctrlreg + TH1520_CTRL_MSTR); + break; + case 2: writel(0x03080020, ctrlreg + TH1520_CTRL_MSTR); - else + break; + default: return -EINVAL; + } writel(0x00003030, ctrlreg + TH1520_CTRL_MRCTRL0); writel(0x0002d90f, ctrlreg + TH1520_CTRL_MRCTRL1); @@ -479,7 +485,8 @@ static int th1520_ddr_ctrl_init(void __iomem *ctrlreg, struct th1520_ddr_fw *fw) switch (fw->bitwidth) { case 64: - writel(0x00040018, ctrlreg + TH1520_CTRL_ADDRMAP0); + writel(fw->ranknum == 2 ? 0x00040018 : 0x0004001f, + ctrlreg + TH1520_CTRL_ADDRMAP0); writel(0x00090909, ctrlreg + TH1520_CTRL_ADDRMAP1); writel(0x00000000, ctrlreg + TH1520_CTRL_ADDRMAP2); writel(0x01010101, ctrlreg + TH1520_CTRL_ADDRMAP3); -- 2.55.0
