Hi Cunhao,
On 10/19/2026 9:31 AM, Cunhao Lu via B4 Relay wrote:
> From: Cunhao Lu <[email protected]>
>
> The shared SDRAM decoder treats type 10 as DDR5 and uses the wrong
> bank count for LPDDR5X. On the 4 GiB OK3572-C, register values
> 0x100043c1 and 0x30001001 therefore produce a size of 1 GiB.
>
> Define LPDDR5X as type 10 and DDR5 as type 11. Apply the existing
> LPDDR5 bank decoding to LPDDR5X so the same register values yield
> 4 GiB. The type values match include/soc/rockchip/rockchip_grf.h in
> the kernel-6.12 sources of Forlinx OK3572-C BSP Alpha1.
>
> Signed-off-by: Cunhao Lu <[email protected]>
> ---
> This patch fixes LPDDR5X capacity decoding in Rockchip's shared SDRAM
> decoder.
>
> The geometry registers captured on a Forlinx OK3572-C with 4 GiB of
> LPDDR5X are 0x100043c1 and 0x30001001. The current decoder labels type
> 10 as DDR5 and uses the generic bank calculation. With the bank bit
> set, it assumes four banks instead of 16 and reports only 1 GiB.
>
> Define LPDDR5X as type 10 and DDR5 as type 11, following the Rockchip
> type definitions in Forlinx OK3572-C BSP Alpha1. Use the existing
> LPDDR5 bank calculation for LPDDR5X so the captured register values
> decode to the correct 4 GiB capacity.
>
> The fix applies to mainline independently of the RK3572 SoC and board
> support.
>
> Host-side validation of the decoder with the captured register values
> reproduced 1 GiB before the fix and returned 4 GiB after it. Regression
> checks for eight other memory type codes produced the same results
> before and after the fix, with no UBSan errors.
> ---
> arch/arm/include/asm/arch-rockchip/sdram.h | 3 ++-
> arch/arm/mach-rockchip/sdram.c | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h
> b/arch/arm/include/asm/arch-rockchip/sdram.h
> index 476fc1c4e..f5a213fde 100644
> --- a/arch/arm/include/asm/arch-rockchip/sdram.h
> +++ b/arch/arm/include/asm/arch-rockchip/sdram.h
> @@ -14,7 +14,8 @@ enum {
> LPDDR4 = 7,
> LPDDR4X = 8,
> LPDDR5 = 9,
> - DDR5 = 10,
> + LPDDR5X = 10,
> + DDR5 = 11,
We should probably just drop the DDR5 symbol, and could possible also
add a DDR2 symbol. DRAM init blobs likely use something like following:
switch (dram_type) {
case 0:
return "DDR4";
case 2:
return "DDR2";
case 3:
return "DDR3";
case 5:
return "LPDDR2";
case 6:
return "LPDDR3";
case 7:
return "LPDDR4";
case 8:
return "LPDDR4X";
case 9:
return "LPDDR5";
case 10:
return "LPDDR5X";
default:
return "Unknown Device";
}
> UNUSED = 0xFF
> };
>
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 2e404df1b..b58919137 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -403,8 +403,8 @@ size_t rockchip_sdram_size(phys_addr_t reg)
> cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
> SYS_REG_COL_MASK);
> cs1_col = cs0_col;
> - if (dram_type == LPDDR5)
> - /* LPDDR5: 0:8bank(bk=3), 1:16bank(bk=4) */
> + if (dram_type == LPDDR5 || dram_type == LPDDR5X)
> + /* LPDDR5/LPDDR5X: 0:8bank(bk=3), 1:16bank(bk=4) */
This seem to be correct and fixes size detection on my OK3572-C board
when the dram info from rk atags are ignored.
With the DDR5 symbol dropped this is,
Reviewed-by: Jonas Karlman <[email protected]>
Regards,
Jonas
> bk = 3 + ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) &
> SYS_REG_BK_MASK);
> else
>
> ---
> base-commit: 8d534cec0cc0109a37c0ded8854da03f1526dc0e
> change-id: 20261019-lpddr5x-size-fix-fbe1c1a168de
>
> Best regards,
> --
> Cunhao Lu <[email protected]>
