On Tue, 27 Oct 2026 17:24:33 +0800, Cooper Huang <[email protected]> wrote: > At high SPI clock frequencies, the controller must delay the sampling > of the read data, and the right delay depends on the board. Port the > read timing calibration from the Linux driver: golden data is read at > HCLK/16, then the timing settings of each HCLK divider, from the > fastest one allowed down to HCLK/5, are scanned until the reads match. > > Until the calibration is done, the flash is accessed at HCLK/16, as in > Linux, since faster settings may not work without the timing > compensation. If no setting passes, or the calibration cannot be done, > the flash stays at HCLK/16 with a warning. > > [...]
Reviewed-by: Tan Siewert <[email protected]> -- Tan Siewert <[email protected]>
