On Thu, Oct 29, 2026 at 03:57:42AM -0700, Abhilash V wrote: > Use Shikra fixed pre-DDR memory map when enabling caches in > SPL. Allocate page tables from the early malloc-F heap and > select the board map through a common Qualcomm hook. > > Signed-off-by: Abhilash V <[email protected]> [snip] > +/* > + * SPL platforms whose pre-DRAM address map differs from the common Qualcomm > + * map may override this hook. > + */ > +struct mm_region *__weak qcom_spl_mem_map(void) > +{ > + return NULL; > +} [snip] > @@ -192,7 +208,11 @@ void enable_caches(void) > > gd->arch.tlb_fillptr = tlb_addr; > > - build_mem_map(); > + spl_mem_map = qcom_spl_mem_map(); > + if (spl_mem_map) > + mem_map = spl_mem_map; > + else > + build_mem_map();
This is kind of odd. Which pre-requisite series brings this in? I wonder if a better abstraction would help, and if this is still the right way to go, the weak part should come in then. -- Tom
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