Consolidate common SpacemiT K1 U-Boot device tree configuration into spacemit-k1-u-boot.dtsi, replacing the MusePi Pro and Banana Pi F3 specific overlays with a shared K1 configuration.
Separate the Binman layout and DDR firmware packaging into spacemit-k1-binman.dtsi, keeping image generation independent of board-specific bring-up. Keep common clock, UART, I2C, GPIO, and pinctrl settings in the shared DTSI to support SPL initialization and reduce duplicated board-specific configuration. Move the I2C8 regulator configuration to dts/upstream so regulators can be mapped by name to the corresponding nodes in the board device trees. These changes provide a cleaner foundation for migrating peripheral configuration to the upstream device trees while minimizing duplicated settings across SpacemiT K1 boards. Cc: Dave Klotz <[email protected]> Cc: Eric Chung <[email protected]> Cc: Hung-Chun Tseng <[email protected]> Cc: E Shattow <[email protected]> Cc: Yixun Lan <[email protected]> Signed-off-by: Anand Moon <[email protected]> --- arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi | 121 ------------------ arch/riscv/dts/spacemit-k1-binman.dtsi | 29 +++++ ...ro-u-boot.dtsi => spacemit-k1-u-boot.dtsi} | 80 +++++------- 3 files changed, 59 insertions(+), 171 deletions(-) delete mode 100644 arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi create mode 100644 arch/riscv/dts/spacemit-k1-binman.dtsi rename arch/riscv/dts/{k1-musepi-pro-u-boot.dtsi => spacemit-k1-u-boot.dtsi} (66%) diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi deleted file mode 100644 index 3077cdee55d..00000000000 --- a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi +++ /dev/null @@ -1,121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2026 RISCstar Ltd. - */ - -#include "binman.dtsi" - -/ { - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x80000000>; - }; -}; - -&uart0 { - bootph-pre-ram; -}; - -&osc_32k { - bootph-pre-ram; -}; - -&vctcxo_1m { - bootph-pre-ram; -}; - -&vctcxo_3m { - bootph-pre-ram; -}; - -&vctcxo_24m { - bootph-pre-ram; -}; - -&syscon_mpmu { - bootph-pre-ram; -}; - -&pll { - bootph-pre-ram; -}; - -&syscon_apmu { - bootph-pre-ram; -}; - -&syscon_apbc { - bootph-pre-ram; -}; - -&i2c2 { - bootph-pre-ram; - - eeprom@50 { - bootph-pre-ram; - }; -}; - -/* - * The kernel pmic@41 nodes use the standard regulator-* properties only; - * U-Boot's regulator framework looks up suppliers by `regulator-name`. - * Carry the U-Boot-specific names (vdd_core / vdd_1v8 / vdd_1v8_mmc) here - * so SPL can program the bucks that DDR training depends on. - */ -&i2c8 { - bootph-pre-ram; - - pmic@41 { - bootph-pre-ram; - - regulators { - buck1 { - regulator-name = "vdd_core"; - bootph-pre-ram; - }; - - buck3 { - regulator-name = "vdd_1v8"; - bootph-pre-ram; - }; - - aldo1 { - regulator-name = "vdd_1v8_mmc"; - bootph-pre-ram; - }; - }; - }; -}; - -&emmc { - bootph-pre-ram; - max-frequency = <204800000>; -}; - -&sdhci0 { - bootph-pre-ram; - max-frequency = <204800000>; -}; - -&binman { - u-boot-spl-ddr { - type = "section"; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; - - u-boot-spl { - }; - - ddr-fw { - type = "blob"; - filename = "ddr_fw.bin"; - align = <64>; - }; - - u-boot-any { - type = "section"; - size = <0>; - offset = <0>; - }; - }; -}; diff --git a/arch/riscv/dts/spacemit-k1-binman.dtsi b/arch/riscv/dts/spacemit-k1-binman.dtsi new file mode 100644 index 00000000000..2ff6bd2cc43 --- /dev/null +++ b/arch/riscv/dts/spacemit-k1-binman.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2026 RISCstar Ltd. + */ + +#include "binman.dtsi" + +&binman { + u-boot-spl-ddr { + type = "section"; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + }; + + ddr-fw { + type = "blob"; + filename = "ddr_fw.bin"; + align = <64>; + }; + + u-boot-any { + type = "section"; + size = <0>; + offset = <0>; + }; + }; +}; diff --git a/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi b/arch/riscv/dts/spacemit-k1-u-boot.dtsi similarity index 66% rename from arch/riscv/dts/k1-musepi-pro-u-boot.dtsi rename to arch/riscv/dts/spacemit-k1-u-boot.dtsi index d6299c96949..94107da3e5f 100644 --- a/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi +++ b/arch/riscv/dts/spacemit-k1-u-boot.dtsi @@ -4,12 +4,13 @@ */ #include <dt-bindings/clock/spacemit,k1-syscon.h> -#include "binman.dtsi" / { aliases { console = &uart0; serial0 = &uart0; + mmc0 = &emmc; + mmc1 = &sdhci0; }; chosen { @@ -83,77 +84,56 @@ }; }; -&i2c8 { +&qspi { bootph-pre-ram; status = "okay"; - pmic@41 { + flash@0 { + reg = <0>; + spi-max-frequency = <50000000>; bootph-pre-ram; - compatible = "spacemit,p1"; - reg = <0x41>; - interrupts = <64>; status = "okay"; - - regulators { - buck1 { - bootph-pre-ram; - regulator-name = "vdd_core"; - }; - - buck3_1v8: buck3 { - bootph-pre-ram; - regulator-name = "vdd_1v8"; - }; - - aldo1 { - bootph-pre-ram; - regulator-name = "vdd_1v8_mmc"; - }; - - }; }; }; -&qspi { +&qspi_cfg { bootph-pre-ram; - status = "okay"; - - flash@0 { - bootph-pre-ram; - status = "okay"; - }; }; &emmc { + compatible = "spacemit,k1-sdhci"; bootph-pre-ram; max-frequency = <204800000>; + status = "okay"; }; &sdhci0 { + compatible = "spacemit,k1-sdhci"; bootph-pre-ram; - cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + pinctrl-names = "default", "uhs"; max-frequency = <204800000>; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + status = "okay"; }; -&binman { - u-boot-spl-ddr { - type = "section"; - filename = "u-boot-spl-ddr.bin"; - pad-byte = <0xff>; +&pinctrl { + bootph-pre-ram; + status = "okay"; +}; - u-boot-spl { - }; +&gpio { + bootph-pre-ram; + status = "okay"; +}; - ddr-fw { - type = "blob"; - filename = "ddr_fw.bin"; - align = <64>; - }; +&mmc1_cfg { + bootph-pre-ram; +}; - u-boot-any { - type = "section"; - size = <0>; - offset = <0>; - }; - }; +&mmc1_uhs_cfg { + bootph-pre-ram; }; + +/* Keep the existing binman layout and DDR firmware section. */ +#include "spacemit-k1-binman.dtsi" -- 2.56.0
