Select the QUP and SDCC2 source table entry before enabling its PLL. UART rates from GPLL0_AUX2 must not vote GPLL6. SDCC2 needs a GPLL7 vote only for its GPLL7 table entry. This avoids enabling unrelated PLLs during SPL clock setup.
Signed-off-by: Abhilash V <[email protected]> --- drivers/clk/qcom/clock-shikra.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clock-shikra.c b/drivers/clk/qcom/clock-shikra.c index a74d529f4cf..ae360894082 100644 --- a/drivers/clk/qcom/clock-shikra.c +++ b/drivers/clk/qcom/clock-shikra.c @@ -152,8 +152,9 @@ static ulong shikra_set_rate(struct clk *clk, ulong rate) freq->pre_div, freq->m, freq->n, freq->src, 8); return freq->freq; case GCC_SDCC2_APPS_CLK: - clk_enable_gpll0(priv->base, &gpll7_vote_clk); freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + if (freq->src == CFG_CLK_SRC_GPLL7) + clk_enable_gpll0(priv->base, &gpll7_vote_clk); clk_rcg_set_rate_mnd(priv->base, GCC_SDCC2_APPS_CLK_CMD_RCGR, freq->pre_div, freq->m, freq->n, freq->src, 8); return freq->freq; -- 2.34.1
