In RMII mode the IOMUXC GPR[1] setup always selects the internally
generated reference clock, ignoring the snps,rmii_refclk_ext property.
On boards where the 50 MHz clock comes from an external source, the PHY
auto-negotiation times out:
Waiting for PHY auto negotiation to complete...... TIMEOUT !
phy_startup() failed: -110
Set ENET_QOS_CLK_TX_CLK_SEL only if snps,rmii_refclk_ext is missing, as
Linux does.
Signed-off-by: Dario Binacchi <[email protected]>
---
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index b7b3702041ee..065a946f2855 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -10,6 +10,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <div64.h>
+#include <dm/read.h>
#include <errno.h>
#include <linux/bitops.h>
#include <linux/delay.h>
@@ -852,9 +853,11 @@ static int imx8mp_eqos_interface_init(struct udevice *dev,
break;
case PHY_INTERFACE_MODE_RMII:
setbits_le32(&gpr->gpr[1],
- IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
+ if (!dev_read_bool(dev, "snps,rmii_refclk_ext"))
+ setbits_le32(&gpr->gpr[1],
+
IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL);
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
---
base-commit: 3973f3c4d24df75ca90d7c0a9f03e5e5c9b48f32
branch: imx8mp-eqos-rmii-refclk-ext
--
2.43.0
