On 2026-10-11T22:28:36, Jonas Karlman <[email protected]> wrote: > clk: rockchip: pll: Use PLL_FIXED_MODE flag on RK3588/RK3576 PPLL > > The PPLL on RK3588 and RK3576 has no PLL mode register and cannot switch > between slow, deep slow or normal mode. > > Extend ROCKCHIP_PLL_FIXED_MODE support to the pll_rk3588 type and mark > both PPLLs with this flag. Skip mode register writes when changing rates > and treat the PLLs as operating in normal mode when reading rates. > > Signed-off-by: Jonas Karlman <[email protected]> > Reviewed-by: Quentin Schulz <[email protected]> > > arch/arm/include/asm/arch-rockchip/clock.h | 2 +- > drivers/clk/rockchip/clk_pll.c | 21 +++++++++++++-------- > drivers/clk/rockchip/clk_rk3576.c | 3 ++- > drivers/clk/rockchip/clk_rk3588.c | 3 ++- > 4 files changed, 18 insertions(+), 11 deletions(-)
Reviewed-by: Simon Glass <[email protected]>
