Hi Jonas,
On 2026-10-11T22:28:36, Jonas Karlman <[email protected]> wrote:
> clk: rockchip: rk3588: Set ACLK_BUS_ROOT to 375 MHz
>
> The clock driver always reports ACLK_BUS_ROOT rate as 375 MHz. However,
> the clock is initialized to use GPLL as parent and a target rate of
> 300 MHz, with GPLLs typicall 1.188 GHz rate the clock ends up at 297 MHz.
'typicall' should be 'typical', here and in the next paragraph, and
'GPLLs' and 'CPLLs' should be 'GPLL's' and 'CPLL's'. Please can you
fix these if you send a v3.
The code change looks fine to me. It matches the assigned-clock-rates
value in the SoC DT and the 375 MHz that rk3588_clk_get_rate()
reports.
>
> Change to use CPLL as parent and request a 375 MHz rate, the same rate
> that is already being reported by the driver and what the SoC DT uses in
> assigned-clock-rates. With CPLLs typicall 1.5 GHz rate, this matches the
> parent and rate Linux typically ends up using for this clock.
>
> Fixes: 716ed2a8c0bb ("clk: rockchip: rk3588: add hardcoded assigned clocks
> values")
> Signed-off-by: Jonas Karlman <[email protected]>
> Reviewed-by: Quentin Schulz <[email protected]>
>
> drivers/clk/rockchip/clk_rk3588.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Regards,
Simon
