On 11/4/26 9:20 AM, Clément Le Goffic wrote:
Hello Clement,
On 11/3/26 4:53 PM, Marek Vasut wrote:
On 11/3/26 4:01 PM, Clément Le Goffic wrote:
The generic counter shared by the Cortex-A720AE and Cortex-R52 cores is
stopped at reset. With U-Boot as the first stage on the RSIP-M, nothing
starts it before the Cortex-R52 cores are released, so their timers never
advance and a timed wait such as a Zephyr k_sleep() blocks forever.
Only CPU in secure mode can start this counter. Zephyr on R52 has no control on
the CPU mode so can't start it if it is in secure mode. Start it there
in u-boot IPL.
Program the counter frequency and enable it before any other
initialization, through the RSIP-M alias of the counter frame.
Also fix the advertised frequency as the counter counts by H'10 every
clock edge of its reference clock SASYNCD1_RT_MAIN (66.666667 MHz)
66.666667 * 16 = 1066.666667 -> 1066666667.
Signed-off-by: Clément Le Goffic <[email protected]>
---
Changes in v2:
- Explain in the commit message why the RSIP-M U-Boot starts the counter
and the CONFIG_SYS_CLK_FREQ change
- Drop the Assisted-by trailer
Is this patch no longer generated by AI ?
Tom told me that it is discouraged to use AI + it breaks checkpatch:
https://lore.kernel.org/u-boot/20261026210850.GK646438@bill-the-cat/
Indeed I could have mention it and sharing this link.
Is this still generated code ?
