Add the DDR controller node and mark the UART, I2C EEPROM and required clock and reset providers for use before DRAM initialization.
Add a binman description for spl/u-boot-spl-mkimage.bin, combining SPL with the external LPDDR5 PMU IMEM firmware and wrapping the payload in a SpacemiT K3 boot image header. Signed-off-by: Junhui Liu <[email protected]> --- arch/riscv/dts/spacemit-k3-binman.dtsi | 24 +++++++++++++++ arch/riscv/dts/spacemit-k3-u-boot.dtsi | 54 ++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/arch/riscv/dts/spacemit-k3-binman.dtsi b/arch/riscv/dts/spacemit-k3-binman.dtsi index f1c1c3ee6fd..3f77868a90c 100644 --- a/arch/riscv/dts/spacemit-k3-binman.dtsi +++ b/arch/riscv/dts/spacemit-k3-binman.dtsi @@ -4,3 +4,27 @@ */ #include "binman.dtsi" + +&binman { +#ifdef CONFIG_SPL + spl-img { + filename = "spl/u-boot-spl-mkimage.bin"; + + mkimage { + args = "-T", "smtimage", "-n", "k3"; + + u-boot-spl-ddr { + type = "section"; + + u-boot-spl { + }; + + lpddr5-imem { + filename = "lpddr5_imem.bin"; + type = "blob-ext"; + }; + }; + }; + }; +#endif +}; diff --git a/arch/riscv/dts/spacemit-k3-u-boot.dtsi b/arch/riscv/dts/spacemit-k3-u-boot.dtsi index 352e85e7de8..0976b2647b5 100644 --- a/arch/riscv/dts/spacemit-k3-u-boot.dtsi +++ b/arch/riscv/dts/spacemit-k3-u-boot.dtsi @@ -4,3 +4,57 @@ */ #include "spacemit-k3-binman.dtsi" + +&{/soc} { + ddrc@cb000000 { + compatible = "spacemit,k3-ddrc"; + reg = <0x0 0xcb000000 0x0 0x01000000>, + <0x0 0xcc000000 0x0 0x01000000>; + spacemit,apmu = <&syscon_apmu 0x4e8>; + bootph-pre-ram; + }; +}; + +&i2c2 { + bootph-pre-ram; + + eeprom@50 { + bootph-pre-ram; + }; +}; + +&osc_32k { + bootph-pre-ram; +}; + +&pll { + bootph-pre-ram; +}; + +&syscon_apbc { + bootph-pre-ram; +}; + +&syscon_apmu { + bootph-pre-ram; +}; + +&syscon_mpmu { + bootph-pre-ram; +}; + +&uart0 { + bootph-pre-ram; +}; + +&vctcxo_1m { + bootph-pre-ram; +}; + +&vctcxo_24m { + bootph-pre-ram; +}; + +&vctcxo_3m { + bootph-pre-ram; +}; -- 2.56.0
