The ACLINT specification [1] describes multiple components: 2 of which are an M-mode timer and a MSWI device for M-mode sofware interrupts. The specification was never ratified [2], as systems with AIA have an M-mode IMSIC that provides software interrupts in M-mode. Some hardware implement both components, while others (like Tensorrent Ascalon based SoCs) drop the MSWI funcitonality and rely on the M-mode IMSIC.
The CONFIG_RISCV_ACLINT symbol currently is used to pick both aclint_timer.o (which covers the timer functionality) and aclint_ipi.o (which covers the mswi software interrupts functionality). Introduce a new symbol called CONFIG_RISCV_ACLINT_IPI that SoCs can pick if they rely on the ACLINT for M mode IPI functionality. All boards that currently pick/imply the CONFIG_RISCV_ACLINT symbol have been updated to also pick this newly added symbol. [1] https://github.com/riscvarchive/riscv-aclint/blob/4e570bfd3201f2c09e5afd290b5091526b0f099a/riscv-aclint.adoc [2] https://lists.riscv.org/g/tech-aia/topic/connections_between_aia_and/107177435 Signed-off-by: Anirudh Srinivasan <[email protected]> --- arch/riscv/Kconfig | 12 ++++++++++++ arch/riscv/cpu/fu540/Kconfig | 1 + arch/riscv/cpu/fu740/Kconfig | 1 + arch/riscv/cpu/generic/Kconfig | 2 ++ arch/riscv/cpu/jh7110/Kconfig | 1 + arch/riscv/cpu/k1/Kconfig | 2 ++ arch/riscv/cpu/th1520/Kconfig | 2 ++ arch/riscv/lib/Makefile | 2 +- board/openpiton/riscv64/Kconfig | 1 + board/sipeed/maix/Kconfig | 1 + 10 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 386241efd4a..17194f9f6ac 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -404,6 +404,18 @@ config SPL_RISCV_ACLINT The RISC-V ACLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config RISCV_ACLINT_IPI + bool + depends on RISCV_ACLINT + help + Use the MSWI block in ACLINT for IPI in M-Mode U-boot. + +config SPL_RISCV_ACLINT_IPI + bool + depends on SPL_RISCV_ACLINT + help + Use the MSWI block in ACLINT for IPI in M-Mode U-boot SPL. + config SIFIVE_CACHE bool help diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index f2934cb33e7..87a810ad2e0 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -12,6 +12,7 @@ config SIFIVE_FU540 imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply SPL_RISCV_ACLINT + imply SPL_RISCV_ACLINT_IPI imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index 66f9a8d5fa5..05158b8d023 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -12,6 +12,7 @@ config SIFIVE_FU740 imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply SPL_RISCV_ACLINT + imply SPL_RISCV_ACLINT_IPI imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig index 2baba229923..0b607627739 100644 --- a/arch/riscv/cpu/generic/Kconfig +++ b/arch/riscv/cpu/generic/Kconfig @@ -12,6 +12,8 @@ config GENERIC_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply RISCV_ACLINT if RISCV_MMODE imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE + imply RISCV_ACLINT_IPI if RISCV_MMODE + imply SPL_RISCV_ACLINT_IPI if SPL_RISCV_MMODE imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index fa47e55226e..20ce79e51b6 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -18,6 +18,7 @@ config STARFIVE_JH7110 select PINCTRL_STARFIVE_JH7110 imply SMP imply SPL_RISCV_ACLINT + imply SPL_RISCV_ACLINT_IPI imply SIFIVE_CACHE imply SPL_SYS_MALLOC_CLEAR_ON_INIT imply SPL_LOAD_FIT diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig index b155535658d..d5e17c56bda 100644 --- a/arch/riscv/cpu/k1/Kconfig +++ b/arch/riscv/cpu/k1/Kconfig @@ -16,6 +16,8 @@ config SPACEMIT_K1 imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply RISCV_ACLINT if RISCV_MMODE imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE + imply RISCV_ACLINT_IPI if RISCV_MMODE + imply SPL_RISCV_ACLINT_IPI if SPL_RISCV_MMODE imply CMD_CPU imply DM_RESET imply SPL_CPU diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig index a02f5f24906..59720fd6c5d 100644 --- a/arch/riscv/cpu/th1520/Kconfig +++ b/arch/riscv/cpu/th1520/Kconfig @@ -17,6 +17,8 @@ config THEAD_TH1520 imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply RISCV_ACLINT if RISCV_MMODE imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE + imply RISCV_ACLINT_IPI if RISCV_MMODE + imply SPL_RISCV_ACLINT_IPI if SPL_RISCV_MMODE imply CMD_CPU imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index a527b3e9ae3..a4f2968f05f 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -15,7 +15,7 @@ obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o obj-$(CONFIG_SYS_CACHE_THEAD_CMO) += thead_cmo.o ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y) -obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o +obj-$(CONFIG_$(PHASE_)RISCV_ACLINT_IPI) += aclint_ipi.o obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o else obj-$(CONFIG_SBI) += sbi.o diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig index b646aa8cbb2..5be8c77b37e 100644 --- a/board/openpiton/riscv64/Kconfig +++ b/board/openpiton/riscv64/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CPU_RISCV imply RISCV_TIMER imply SPL_RISCV_ACLINT + imply SPL_RISCV_ACLINT_IPI imply CMD_CPU imply SPL_CPU imply SPL_SMP diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig index d34ea4be71f..0350eb9c01e 100644 --- a/board/sipeed/maix/Kconfig +++ b/board/sipeed/maix/Kconfig @@ -35,6 +35,7 @@ config BOARD_SPECIFIC_OPTIONS imply DM_SERIAL imply SIFIVE_SERIAL imply RISCV_ACLINT + imply RISCV_ACLINT_IPI imply POWER_DOMAIN imply SIMPLE_PM_BUS imply CLK_K210 -- 2.43.0
