Add the EMAC0 AXI, slave AHB, PHY AUX and PTP gate clocks, the
EMAC0 GDSC, and rate-setting for the PHY AUX and PTP clocks.
Taken from 08c51ceb12f7
("clk: qcom: add the GCC driver for sa8775p")
Signed-off-by: Deepak G <[email protected]>
---
drivers/clk/qcom/clock-qcom.h | 1 +
drivers/clk/qcom/clock-sa8775p.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
index 32ecda3f5f1..ecbe3833bcf 100644
--- a/drivers/clk/qcom/clock-qcom.h
+++ b/drivers/clk/qcom/clock-qcom.h
@@ -20,6 +20,7 @@
#define CFG_CLK_SRC_GPLL0_ODD (3 << 8)
#define CFG_CLK_SRC_GPLL6 (4 << 8)
#define CFG_CLK_SRC_GPLL7 (3 << 8)
+#define CFG_CLK_SRC_GPLL7_EMAC0 (2 << 8)
#define CFG_CLK_SRC_GPLL4 (5 << 8)
#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
#define CFG_CLK_SRC_MASK (7 << 8)
diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c
index fa341d05f69..fd495b73635 100644
--- a/drivers/clk/qcom/clock-sa8775p.c
+++ b/drivers/clk/qcom/clock-sa8775p.c
@@ -27,6 +27,9 @@
#define APCS_GPLL9_STATUS 0x9000
#define APCS_GPLLX_ENA_REG 0x4b028
+#define EMAC0_PHY_AUX_CLK_CMD_RCGR 0xb6028
+#define EMAC0_PTP_CLK_CMD_RCGR 0xb6060
+
#define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10)
#define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11)
#define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12)
@@ -101,6 +104,19 @@ static const struct pll_vote_clk gpll9_vote_clk = {
.vote_bit = BIT(9),
};
+/* EMAC0 PHY AUX clock frequency table */
+static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = {
+ F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+ { }
+};
+
+/* EMAC0 PTP clock frequency table */
+static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
+ F(125000000, CFG_CLK_SRC_GPLL7_EMAC0, 8, 0, 0),
+ F(230400000, CFG_CLK_SRC_GPLL4, 3.5, 0, 0),
+ { }
+};
+
static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -140,6 +156,14 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate)
case GCC_UFS_PHY_PHY_AUX_CLK:
clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0,
CFG_CLK_SRC_CXO);
return 19200000;
+ case GCC_EMAC0_PHY_AUX_CLK:
+ clk_rcg_set_rate(priv->base, EMAC0_PHY_AUX_CLK_CMD_RCGR, 0,
CFG_CLK_SRC_CXO);
+ return 19200000;
+ case GCC_EMAC0_PTP_CLK:
+ freq = qcom_find_freq(ftbl_gcc_emac0_ptp_clk_src, rate);
+ clk_rcg_set_rate_mnd(priv->base, EMAC0_PTP_CLK_CMD_RCGR,
+ freq->pre_div, freq->m, freq->n,
freq->src, 16);
+ return freq->freq;
case GCC_SDCC1_APPS_CLK:
freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate);
@@ -209,6 +233,12 @@ static const struct gate_clk sa8775p_clks[] = {
/* SDCC1 clocks */
GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x2000c, BIT(0), 0x2000c),
GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x20004, BIT(0), 0x20004),
+
+ /* EMAC0 clocks */
+ GATE_CLK_POLLED(GCC_EMAC0_AXI_CLK, 0xb6018, BIT(0), 0xb6018),
+ GATE_CLK_POLLED(GCC_EMAC0_SLV_AHB_CLK, 0xb6020, BIT(0), 0xb6020),
+ GATE_CLK_POLLED(GCC_EMAC0_PHY_AUX_CLK, 0xb6024, BIT(0), 0xb6024),
+ GATE_CLK_POLLED(GCC_EMAC0_PTP_CLK, 0xb6040, BIT(0), 0xb6040),
};
static int sa8775p_enable(struct clk *clk)
@@ -285,6 +315,7 @@ static const struct qcom_reset_map sa8775p_gcc_resets[] = {
static const struct qcom_power_map sa8775p_gdscs[] = {
[UFS_PHY_GDSC] = { .reg = 0x83004, .flags = RETAIN_FF_ENABLE |
POLL_CFG_GDSCR },
[USB30_PRIM_GDSC] = { .reg = 0x1B004, .flags = RETAIN_FF_ENABLE |
POLL_CFG_GDSCR },
+ [EMAC0_GDSC] = { .reg = 0xb6004, .flags = RETAIN_FF_ENABLE |
POLL_CFG_GDSCR },
};
static struct msm_clk_data sa8775_gcc_data = {
---
base-commit: 84cc3bc1c6d4b6042ad8d2dd565f881d46c25507
change-id: 20261103-emac_clock-a06461d02699
prerequisite-change-id: 20261103-lemans-ethernet-c5fcad136deb:v2
Best regards,
--
Deepak G <[email protected]>
