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PATMOS 2011
21st International Workshop on Power and Timing Modeling,
Optimization and Simulation
September, 2011,
Madrid, Spain
http://www.patmos-conf.org
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CALL FOR PAPERS
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ABOUT PATMOS:
PATMOS 2011 is the 21st in a series of international workshops. The
PATMOS meeting has evolved into a leading scientific event where
industry and academia meet to discuss power and timing aspects in modern
integrated circuit and system design. Both Universities and Companies
are invited to participate.
The PATMOS objective is to provide a forum to discuss and investigate
emerging challenges in methodologies and tools for the design of
upcoming generations of integrated circuits and systems, including
reconfigurable hardware such as FPGA’s. The technical program will focus
on timing, performance and power consumption as well as architectural
aspects with particular emphasis on modeling, design, characterization,
analysis and optimization.
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PROGRAM TRACKS:
1. Timing and Performance
- Methodologies and tools for the analysis, design and verification of
timing and performance properties of integrated circuits and systems at
all levels of abstraction;
- Variability and statistical timing analysis;
- Design for yield, design for manufacturability;
- Special timing or performance related topics, e.g. crosstalk,
synchronization, GALS, side-channel attacks.
2. Low Power and Thermal-aware Design
- Design techniques for low power circuits and systems at all levels of
abstraction;
- Methods and tools for analysis and characterization of power
consumption;
- Power Estimation and Optimization;
- Low power Architectures and System level Techniques;
- Special power related topics, e.g. low voltage, leakage power, power
grid, interconnect power, clock tree power, power aware test pattern
generation, green computing;
- Thermal-aware circuit and system design;
- Polices for thermal optimization;
- Temperature estimation and thermal sensors.
3. Reliability and Technology Variations
- Modeling and simulation in the presence of on-chip variability;
- Variation-aware circuit design;
- Reliability issues in nanoscale circuits;
- Soft errors and radiation hardening;
- Fault tolerance and dependability;
- Resilient circuits.
4. Power and Timing Issues Addressing Specific Technologies
- Reconfigurable Architectures
- Caches and Memory Devices.
- Emerging Memory Technologies, e.g. Phase Change Memories
5. Design Experience and Case Studies
- Examples, test cases, benchmarks or design studies which present
innovative solutions for timing, performance or power consumption
related design challenges.
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IMPORTANT DATES
* Paper submission deadline (EXTENDED): May 25th, 2011
* Special session proposal deadline: May 15th, 2011
* Acceptance notification: June 30th, 2011
* Camera-ready paper due: July 15th, 2011
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SUBMISSION INSTRUCTIONS
Contributions are invited for regular presentations and discussion
sessions. Prospective authors are invited to submit their complete
manuscript, no later than May 25th, 2011, including a 100-word abstract
and illustrations, in A4 camera-ready format, not exceeding 10 pages or
5000 words.
Electronic submission is required and should follow the style of the
final publication. Each paper will be reviewed by at least three program
committee members. In order to maintain a blind review, information
about authors should not be included in the submission.
Paper Format: Submissions should be in camera-ready format, following
the Springer Verlag LNCS series specifications. LATEX instructions can
be located at:
http://www.springer.com/computer/lncs?SGWID=0-164-6-793341-0
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SPECIAL ISSUE
A selection of the best papers will be published in a Special Issue of
IET Circuits, Devices and Systems http://scitation.aip.org/IET-CDS
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TECHNICAL SPONSOR
IEEE Council of Electronic Design Automation (http://www.c-eda.org)
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ORGANIZATION
* General Chairs:
Jose L. Ayala, Complutense Univ., Spain
Manuel Prieto, Complutense Univ., Spain
* Program Chairs:
Gilles Sicard, TIMA Lab, France
Martino Ruggiero, Univ. Bologna, Italy
* Special Sessions Chairs:
Luis Pinuel, Complutense Univ., Spain
Edith Beigne, CEA-LETI, France
* Local Arrangement Chairs
Katzalin Olcoz, Complutense Univ., Spain
Theocharis Theocharides, UNIVCYP, Cyprus
* Publication Chair
Braulio Garcia-Camara, UNICAN, Spain
* Publicity Chair:
Jose I. Hidalgo, Complutense Univ., Spain
* Finance Chair
Fernando Rincon, UCLM, Spain
* Institutional Relations
David Atienza, EPFL, Switzerland
* Steering Committee:
Antonio, J. Acosta
Reiner Hartenstein
Philippe Maurine
Vassilis Paliouras
Diederik Verkest
Nadine Azemard
Jorge Juan-Chico
Jose Monteiro
Christian Piguet
Roberto Zafalon
Joan Figueras
Enrico Macii
Wolfgang Nebel
Dimitrios Soudris
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Jose L. Ayala, PhD E-Mail: [email protected]
Computer Science Faculty Phone: (+34) 91 3947614
Complutense University of Madrid Fax: (+34) 91 3947527
C/ Prof. José García Santesmases, s/n www.dacya.ucm.es/jlayala
28040 Madrid, Spain
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