There is difference in machine descritptions writtem for *ior_scc_scc pattern.
GCC 4.8 branch, *ior_scc_scc pattern is
(define_insn_and_split "*ior_scc_scc"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(ior:SI (match_operator:SI 3 "arm_comparison_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_add_operand" "rIL")])
(match_operator:SI 6 "arm_comparison_operator"
[(match_operand:SI 4 "s_register_operand" "r")
(match_operand:SI 5 "arm_add_operand" "rIL")])))
(clobber (reg:CC CC_REGNUM))]
In GCC 4.9 tunk
(define_insn_and_split "*ior_scc_scc"
[(set (match_operand:SI 0 "s_register_operand" "=Ts")
(ior:SI (match_operator:SI 3 "arm_comparison_operator"
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_add_operand" "rIL")])
(match_operator:SI 6 "arm_comparison_operator"
[(match_operand:SI 4 "s_register_operand" "r")
(match_operand:SI 5 "arm_add_operand" "rIL")])))
(clobber (reg:CC CC_REGNUM))]
Which defines a new constarint "Ts"and gives it general register set
when "it" support is not restriccted
(define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
"For arm_restrict_it the core registers @code{r0}-@code{r7}. GENERAL_REGS
otherwise."
This is the only difference in machinde descriptions. But this does not
fixes the bug. I still count on LRA is able to satisfy the constraint
while reload still fails even in trunk.
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https://bugs.launchpad.net/bugs/1295738
Title:
[4.8 Regression] unable to find a register to spill in class 'LO_REGS'
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