Public bug reported:
>From kernel v4.0, CPU cache topo information is added into sysfs for ARM64, >in which all cores often share one L3 cache such as APM xgene, so cache domain count can be one, and irqbalance will work at oneshot mode. With the following upstream patch, irqbalance can work as before. https://github.com/Irqbalance/irqbalance/commit/4540a34b728780985041d8432e580d8000589c76 ** Affects: irqbalance (Ubuntu) Importance: Undecided Status: New -- You received this bug notification because you are a member of Ubuntu Bugs, which is subscribed to Ubuntu. https://bugs.launchpad.net/bugs/1476512 Title: wily: arm64: irqbalance works at oneshot mode at default To manage notifications about this bug go to: https://bugs.launchpad.net/ubuntu/+source/irqbalance/+bug/1476512/+subscriptions -- ubuntu-bugs mailing list ubuntu-bugs@lists.ubuntu.com https://lists.ubuntu.com/mailman/listinfo/ubuntu-bugs
