Tested with 1.39.0-0ubuntu3 from Artful:
$ apt-cache policy s390-tools
s390-tools:
Installed: 1.39.0-0ubuntu3
Candidate: 1.39.0-0ubuntu3
Version table:
*** 1.39.0-0ubuntu3 500
500 http://us.ports.ubuntu.com/ubuntu-ports artful/main s390x Packages
100 /var/lib/dpkg/status
and it seems to work:
$ lscpumf -c
Perf event counter list for IBM z13
==============================================================================
Raw
event Name Description
------------------------------------------------------------------------------
r0 CPU_CYCLES
Cycle Count.
Counter 0 / Basic Counter Set.
r1 INSTRUCTIONS
Instruction Count.
Counter 1 / Basic Counter Set.
r2 L1I_DIR_WRITES
Level-1 I-Cache Directory Write Count.
Counter 2 / Basic Counter Set.
r3 L1I_PENALTY_CYCLES
Level-1 I-Cache Penalty Cycle Count.
Counter 3 / Basic Counter Set.
r4 L1D_DIR_WRITES
Level-1 D-Cache Directory Write Count.
Counter 4 / Basic Counter Set.
r5 L1D_PENALTY_CYCLES
Level-1 D-Cache Penalty Cycle Count.
Counter 5 / Basic Counter Set.
r20 PROBLEM_STATE_CPU_CYCLES
Problem-State Cycle Count.
Counter 32 / Problem-State Counter Set.
r21 PROBLEM_STATE_INSTRUCTIONS
Problem-State Instruction Count.
Counter 33 / Problem-State Counter Set.
r22 PROBLEM_STATE_L1I_DIR_WRITES
Problem-State Level-1 I-Cache Directory Write Count.
Counter 34 / Problem-State Counter Set.
r23 PROBLEM_STATE_L1I_PENALTY_CYCLES
Problem-State Level-1 I-Cache Penalty Cycle Count.
Counter 35 / Problem-State Counter Set.
r24 PROBLEM_STATE_L1D_DIR_WRITES
Problem-State Level-1 D-Cache Directory Write Count.
Counter 36 / Problem-State Counter Set.
r25 PROBLEM_STATE_L1D_PENALTY_CYCLES
Problem-State Level-1 D-Cache Penalty Cycle Count.
Counter 37 / Problem-State Counter Set.
r40 PRNG_FUNCTIONS
Total number of the PRNG functions issued by the CPU.
Counter 64 / Crypto-Activity Counter Set.
r41 PRNG_CYCLES
Total number of CPU cycles when the DEA/AES coprocessor is
busy performing PRNG functions issued by the CPU.
Counter 65 / Crypto-Activity Counter Set.
r42 PRNG_BLOCKED_FUNCTIONS
Total number of the PRNG functions that are issued by the CPU
and are blocked because the DEA/AES coprocessor is busy
performing a function issued by another CPU.
Counter 66 / Crypto-Activity Counter Set.
r43 PRNG_BLOCKED_CYCLES
Total number of CPU cycles blocked for the PRNG functions
issued by the CPU because the DEA/AES coprocessor is busy
performing a function issued by another CPU.
Counter 67 / Crypto-Activity Counter Set.
r44 SHA_FUNCTIONS
Total number of SHA functions issued by the CPU.
Counter 68 / Crypto-Activity Counter Set.
r45 SHA_CYCLES
Total number of CPU cycles when the SHA coprocessor is busy
performing the SHA functions issued by the CPU.
Counter 69 / Crypto-Activity Counter Set.
r46 SHA_BLOCKED_FUNCTIONS
Total number of the SHA functions that are issued by the CPU
and are blocked because the SHA coprocessor is busy
performing a function issued by another CPU.
Counter 70 / Crypto-Activity Counter Set.
r47 SHA_BLOCKED_CYCLES
Total number of CPU cycles blocked for the SHA functions
issued by the CPU because the SHA coprocessor is busy
performing a function issued by another CPU.
Counter 71 / Crypto-Activity Counter Set.
r48 DEA_FUNCTIONS
Total number of the DEA functions issued by the CPU.
Counter 72 / Crypto-Activity Counter Set.
r49 DEA_CYCLES
Total number of CPU cycles when the DEA/AES coprocessor is
busy performing the DEA functions issued by the CPU.
Counter 73 / Crypto-Activity Counter Set.
r4a DEA_BLOCKED_FUNCTIONS
Total number of the DEA functions that are issued by the CPU
and are blocked because the DEA/AES coprocessor is busy
performing a function issued by another CPU.
Counter 74 / Crypto-Activity Counter Set.
r4b DEA_BLOCKED_CYCLES
Total number of CPU cycles blocked for the DEA functions
issued by the CPU because the DEA/AES coprocessor is busy
performing a function issued by another CPU.
Counter 75 / Crypto-Activity Counter Set.
r4c AES_FUNCTIONS
Total number of AES functions issued by the CPU.
Counter 76 / Crypto-Activity Counter Set.
r4d AES_CYCLES
Total number of CPU cycles when the DEA/AES coprocessor is
busy performing the AES functions issued by the CPU.
Counter 77 / Crypto-Activity Counter Set.
r4e AES_BLOCKED_FUNCTIONS
Total number of AES functions that are issued by the CPU and
are blocked because the DEA/AES coprocessor is busy
performing a function issued by another CPU.
Counter 78 / Crypto-Activity Counter Set.
r4f AES_BLOCKED_CYCLES
Total number of CPU cycles blocked for the AES functions
issued by the CPU because the DEA/AES coprocessor is busy
performing a function issued by another CPU.
Counter 79 / Crypto-Activity Counter Set.
r80 L1D_WRITES_RO_EXCL
Counter:128 Name:L1D_WRITES_RO_EXCL A directory write to the
Level-1 Data cache where the line was originally in a Read-
Only state in the cache but has been updated to be in the
Exclusive state that allows stores to the cache line..
Counter 128 / Extended Counter Set.
r81 DTLB1_WRITES
A translation entry has been written to the Level-1 Data
Translation Lookaside Buffer.
Counter 129 / Extended Counter Set.
r82 DTLB1_MISSES
Level-1 Data TLB miss in progress. Incremented by one for
every cycle a DTLB1 miss is in progress..
Counter 130 / Extended Counter Set.
r83 DTLB1_HPAGE_WRITES
A translation entry has been written to the Level-1 Data
Translation Lookaside Buffer for a one-megabyte page.
Counter 131 / Extended Counter Set.
r84 DTLB1_GPAGE_WRITES
Counter:132 Name:DTLB1_GPAGE_WRITES A translation entry has
been written to the Level-1 Data Translation Lookaside Buffer
for a two-gigabyte page..
Counter 132 / Extended Counter Set.
r85 L1D_L2D_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from the Level-2 Data
cache.
Counter 133 / Extended Counter Set.
r86 ITLB1_WRITES
A translation entry has been written to the Level-1
Instruction Translation Lookaside Buffer.
Counter 134 / Extended Counter Set.
r87 ITLB1_MISSES
Level-1 Instruction TLB miss in progress. Incremented by one
for every cycle an ITLB1 miss is in progress.
Counter 135 / Extended Counter Set.
r88 L1I_L2I_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from the Level-2
Instruction cache.
Counter 136 / Extended Counter Set.
r89 TLB2_PTE_WRITES
A translation entry has been written to the Level-2 TLB Page
Table Entry arrays.
Counter 137 / Extended Counter Set.
r8a TLB2_CRSTE_HPAGE_WRITES
A translation entry has been written to the Level-2 TLB
Combined Region Segment Table Entry arrays for a one-megabyte
large page translation.
Counter 138 / Extended Counter Set.
r8b TLB2_CRSTE_WRITES
A translation entry has been written to the Level-2 TLB
Combined Region Segment Table Entry arrays.
Counter 139 / Extended Counter Set.
r8c TX_C_TEND
A TEND instruction has completed in a constrained
transactional-execution mode.
Counter 140 / Extended Counter Set.
r8d TX_NC_TEND
A TEND instruction has completed in a non-constrained
transactional-execution mode.
Counter 141 / Extended Counter Set.
r8f L1C_TLB1_MISSES
Increments by one for any cycle where a Level-1 cache or
Level-1 TLB miss is in progress..
Counter 143 / Extended Counter Set.
r90 L1D_ONCHIP_L3_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an On-Chip Level-3
cache without intervention.
Counter 144 / Extended Counter Set.
r91 L1D_ONCHIP_L3_SOURCED_WRITES_IV
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an On-Chip Level-3
cache with intervention.
Counter 145 / Extended Counter Set.
r92 L1D_ONNODE_L4_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an On-Node Level-4
cache.
Counter 146 / Extended Counter Set.
r93 L1D_ONNODE_L3_SOURCED_WRITES_IV
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an On-Node Level-3
cache with intervention.
Counter 147 / Extended Counter Set.
r94 L1D_ONNODE_L3_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an On-Node Level-3
cache without intervention.
Counter 148 / Extended Counter Set.
r95 L1D_ONDRAWER_L4_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an On-Drawer Level-4
cache.
Counter 149 / Extended Counter Set.
r96 L1D_ONDRAWER_L3_SOURCED_WRITES_IV
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an On-Drawer Level-3
cache with intervention.
Counter 150 / Extended Counter Set.
r97 L1D_ONDRAWER_L3_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an On-Drawer Level-3
cache without intervention.
Counter 151 / Extended Counter Set.
r98 L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an Off-Drawer Same-
Column Level-4 cache.
Counter 152 / Extended Counter Set.
r99 L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an Off-Drawer Same-
Column Level-3 cache with intervention.
Counter 153 / Extended Counter Set.
r9a L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an Off-Drawer Same-
Column Level-3 cache without intervention.
Counter 154 / Extended Counter Set.
r9b L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an Off-Drawer Far-
Column Level-4 cache.
Counter 155 / Extended Counter Set.
r9c L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an Off-Drawer Far-
Column Level-3 cache with intervention.
Counter 156 / Extended Counter Set.
r9d L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from an Off-Drawer Far-
Column Level-3 cache without intervention.
Counter 157 / Extended Counter Set.
r9e L1D_ONNODE_MEM_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from On-Node memory.
Counter 158 / Extended Counter Set.
r9f L1D_ONDRAWER_MEM_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from On-Drawer memory.
Counter 159 / Extended Counter Set.
ra0 L1D_OFFDRAWER_MEM_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from On-Drawer memory.
Counter 160 / Extended Counter Set.
ra1 L1D_ONCHIP_MEM_SOURCED_WRITES
A directory write to the Level-1 Data cache directory where
the returned cache line was sourced from On-Chip memory.
Counter 161 / Extended Counter Set.
ra2 L1I_ONCHIP_L3_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an On-Chip
Level-3 cache without intervention.
Counter 162 / Extended Counter Set.
ra3 L1I_ONCHIP_L3_SOURCED_WRITES_IV
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an On Chip
Level-3 cache with intervention.
Counter 163 / Extended Counter Set.
ra4 L1I_ONNODE_L4_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an On-Node
Level-4 cache.
Counter 164 / Extended Counter Set.
ra5 L1I_ONNODE_L3_SOURCED_WRITES_IV
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an On-Node
Level-3 cache with intervention.
Counter 165 / Extended Counter Set.
ra6 L1I_ONNODE_L3_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an On-Node
Level-3 cache without intervention.
Counter 166 / Extended Counter Set.
ra7 L1I_ONDRAWER_L4_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an On-Drawer
Level-4 cache.
Counter 167 / Extended Counter Set.
ra8 L1I_ONDRAWER_L3_SOURCED_WRITES_IV
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an On-Drawer
Level-3 cache with intervention.
Counter 168 / Extended Counter Set.
ra9 L1I_ONDRAWER_L3_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an On-Drawer
Level-3 cache without intervention.
Counter 169 / Extended Counter Set.
raa L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an Off-Drawer
Same-Column Level-4 cache.
Counter 170 / Extended Counter Set.
rab L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an Off-Drawer
Same-Column Level-3 cache with intervention.
Counter 171 / Extended Counter Set.
rac L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an Off-Drawer
Same-Column Level-3 cache without intervention.
Counter 172 / Extended Counter Set.
rad L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an Off-Drawer
Far-Column Level-4 cache.
Counter 173 / Extended Counter Set.
rae L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an Off-Drawer
Far-Column Level-3 cache with intervention.
Counter 174 / Extended Counter Set.
raf L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from an Off-Drawer
Far-Column Level-3 cache without intervention.
Counter 175 / Extended Counter Set.
rb0 L1I_ONNODE_MEM_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from On-Node
memory.
Counter 176 / Extended Counter Set.
rb1 L1I_ONDRAWER_MEM_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from On-Drawer
memory.
Counter 177 / Extended Counter Set.
rb2 L1I_OFFDRAWER_MEM_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from On-Drawer
memory.
Counter 178 / Extended Counter Set.
rb3 L1I_ONCHIP_MEM_SOURCED_WRITES
A directory write to the Level-1 Instruction cache directory
where the returned cache line was sourced from On-Chip
memory.
Counter 179 / Extended Counter Set.
rda TX_NC_TABORT
A transaction abort has occurred in a non-constrained
transactional-execution mode.
Counter 218 / Extended Counter Set.
rdb TX_C_TABORT_NO_SPECIAL
A transaction abort has occurred in a constrained
transactional-execution mode and the CPU is not using any
special logic to allow the transaction to complete.
Counter 219 / Extended Counter Set.
rdc TX_C_TABORT_SPECIAL
A transaction abort has occurred in a constrained
transactional-execution mode and the CPU is using special
logic to allow the transaction to complete.
Counter 220 / Extended Counter Set.
r1c0 MT_DIAG_CYCLES_ONE_THR_ACTIVE
Cycle count with one thread active.
Counter 448 / MT-diagnostic Counter Set.
r1c1 MT_DIAG_CYCLES_TWO_THR_ACTIVE
Cycle count with two threads active.
Counter 449 / MT-diagnostic Counter Set.
** Also affects: ubuntu-z-systems
Importance: Undecided
Status: New
** Changed in: ubuntu-z-systems
Status: New => Fix Released
** Changed in: s390-tools (Ubuntu)
Status: New => Fix Released
** Changed in: ubuntu-z-systems
Assignee: (unassigned) => bugproxy (bugproxy)
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https://bugs.launchpad.net/bugs/1683973
Title:
lscpumf: Use of uninitialized value
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