Looking at the kernel source (drivers/gpu/drm/radeon/evergreen_cs.c), it
appears the value:
surf.nby == 1152
is wrong.
Since the layer size is 8847360 bytes and the correct height 1080
pixels, this means you have a stride of 8192 bytes per row (which is
1920 pixels rounded up to 2048, multiplied by 4 bytes per pixel). So in
the least the error message looks buggy: It should not say "1920 1152".
But the trigger for the error also isn't directly related to that...
The trigger for the error is:
/* toffset == texdw[2] << 8 == 0 */
/* depth = 1 */
/* mslice == 1 */
/* surf.layer_size == 8847360 */
if (dim == SQ_TEX_DIM_3D) {
toffset += surf.layer_size * depth;
} else {
toffset += surf.layer_size * mslice;
}
/* toffset == 8847360 */
/* radeon_bo_size(texture) == 4096 */
if (toffset > radeon_bo_size(texture)) {
dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, "
"offset %ld, max layer %d, depth %d, bo size %ld) (%d
%d)\n",
__func__, __LINE__, surf.layer_size,
(unsigned long)texdw[2] << 8, mslice,
depth, radeon_bo_size(texture),
surf.nbx, surf.nby);
return -EINVAL;
}
Those are two very different values. Of course toffset is bigger. I
can't tell if that's a mistake in the kernel logic or an encoding
mistake from mesa (or Xorg).
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https://bugs.launchpad.net/bugs/1791090
Title:
Xorg fails to start with radeon (kernel rejects radeon command stream
from Xorg)
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