git bisect good
cfafe260137418d0265d0df3bb18dc494af2b43e is the first bad commit
commit cfafe260137418d0265d0df3bb18dc494af2b43e
Author: Atish Patra <atish.pa...@wdc.com>
Date: Tue Mar 17 18:11:43 2020 -0700
RISC-V: Add supported for ordered booting method using HSM
Currently, all harts have to jump Linux in RISC-V. This complicates the
multi-stage boot process as every transient stage also has to ensure all
harts enter to that stage and jump to Linux afterwards. It also obstructs
a clean Kexec implementation.
SBI HSM extension provides alternate solutions where only a single hart
need to boot and enter Linux. The booting hart can bring up secondary
harts one by one afterwards.
Add SBI HSM based cpu_ops that implements an ordered booting method in
RISC-V. This change is also backward compatible with older firmware not
implementing HSM extension. If a latest kernel is used with older
firmware, it will continue to use the default spinning booting method.
Signed-off-by: Atish Patra <atish.pa...@wdc.com>
Reviewed-by: Anup Patel <a...@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabb...@google.com>
arch/riscv/kernel/Makefile | 3 ++
arch/riscv/kernel/cpu_ops.c | 10 ++++-
arch/riscv/kernel/cpu_ops_sbi.c | 81 +++++++++++++++++++++++++++++++++++++++++
arch/riscv/kernel/head.S | 26 +++++++++++++
arch/riscv/kernel/smpboot.c | 2 +-
arch/riscv/kernel/traps.c | 2 +-
6 files changed, 121 insertions(+), 3 deletions(-)
create mode 100644 arch/riscv/kernel/cpu_ops_sbi.c
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https://bugs.launchpad.net/bugs/1894613
Title:
risc-v 5.8 kernel oops on ftrace tests
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