** Description changed:
Description:
Invalidation Hint (IH) can be provided for page-selective-within-PASID
invalidations, the Invalidation Hint specifies if the first-level and nested
mappings cached in the paging-structure-caches that controls the specified
address/mask range needs to be invalidated or not. For software usages that
update only the leaf PTEs, the first-level and nested mappings in the
paging-structure-caches can be preserved by specifying the Invalidation Hint
field value of 1.
However, currently our SVM code hardcode IH=0. which is less optimal.
For vSVM, we have already added a generic flag
(IOMMU_INV_ADDR_FLAG_LEAF) to indicate passdown cache invalidate API is
for leaf PTE only. So as long as native SVM is fixed, vSVM could set the
IH w/o code change.
SW needs to obtain statistics of non-leaf paging structure to provide IH
bit.
static void intel_flush_svm_range(struct intel_svm *svm, unsigned long
address,
unsigned long pages, int ih, int gl)
{ struct intel_svm_dev *sdev; rcu_read_lock(); list_for_each_entry_rcu(sdev,
&svm->devs, list) intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
rcu_read_unlock(); }
/* Pages have been freed at this point */
static void intel_invalidate_range(struct mmu_notifier *mn,
struct mm_struct *mm,
unsigned long start, unsigned long end)
{ struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
intel_flush_svm_range(svm, start, (end - start + PAGE_SIZE - 1) >>
VTD_PAGE_SHIFT, 0, 0); }
- Target Kernel: 5.11
+ Target Kernel: TBD
Target Release: 21.04
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https://bugs.launchpad.net/bugs/1878523
Title:
[IOMMU] Provide invalidation hint to IOMMU page selective PASID-based
IOTLB invalidation
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