Only C910, C920 are impacted by Ghostwrite. C906 is impacted by a CPU-
halting bug which cannot be prevented in OpenSBI.

The boards that we support use the C906 core.

** Description changed:

  https://ghostwriteattack.com/riscvuzz.pdf describes that some T-Head
  processors allow unprivileged users to access any physical address due
  to incorrectly implemented vector instructions.
  
  We have published 22.04 and 24.04 images for the Nezha D1 and LicheeRV
  Dock boards. These use the T-Head C906 core mentioned in the
  publication.
  
  The VS field of the mstatus CRC can be used to disable vector
  instructions as described in chapter 3.1.6., "Machine Status Registers
  (mstatus and mstatush)" of the Privileged Architecture Specification
  version 2024-04-11.
  
- On T-Head C906, C908, C910 cores OpenSBI should set the VS field to 0
- (Off) and adjust the published ISA extensions in the device-tree and
- possibly in the misa register.
+ On T-Head C910, C910 cores OpenSBI should set the VS field to 0 (Off)
+ and adjust the published ISA extensions in the device-tree and possibly
+ in the misa register.
  
  We need to check that with this change vector instructions result in a
  trap.

** Description changed:

  https://ghostwriteattack.com/riscvuzz.pdf describes that some T-Head
  processors allow unprivileged users to access any physical address due
  to incorrectly implemented vector instructions.
  
  We have published 22.04 and 24.04 images for the Nezha D1 and LicheeRV
  Dock boards. These use the T-Head C906 core mentioned in the
  publication.
  
  The VS field of the mstatus CRC can be used to disable vector
  instructions as described in chapter 3.1.6., "Machine Status Registers
  (mstatus and mstatush)" of the Privileged Architecture Specification
  version 2024-04-11.
  
- On T-Head C910, C910 cores OpenSBI should set the VS field to 0 (Off)
+ On T-Head C910, C920 cores OpenSBI should set the VS field to 0 (Off)
  and adjust the published ISA extensions in the device-tree and possibly
  in the misa register.
  
  We need to check that with this change vector instructions result in a
  trap.

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https://bugs.launchpad.net/bugs/2076397

Title:
  Ghostwrite mitigation

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