I have failed to produce the reproducer for RISCV - the vectorizer does not kick in for the provided sample:
test.c:13:6: note: vectorized 0 loops in function. test.c:16:18: note: ***** Analysis failed with vector mode DI test.c:20:6: note: vectorized 0 loops in function. test.c:23:25: note: ***** Analysis failed with vector mode DI But reading blogs/documentation[1] points to RISCV having a first-class support for accessing elements of the vector, where as ARM SVE computes offsets array (and that's where the bug is). Conclusion: it is not possible to reproduce the issue with RISCV vector addressing, but for consistency with earlier GCC SRU it would make sense to upload gcc-XX-cross-ports so that the compilers behave consistently. [1] https://fprox.substack.com/p/riscv-vector-extension-part5-1-load-store-memory [2] https://lists.riscv.org/g/tech-vector-ext/attachment/691/0/riscv-v-spec-1.0.pdf -- You received this bug notification because you are a member of Ubuntu Bugs, which is subscribed to Ubuntu. https://bugs.launchpad.net/bugs/2101084 Title: GCC produces wrong code for arm64+sve in some cases To manage notifications about this bug go to: https://bugs.launchpad.net/gcc/+bug/2101084/+subscriptions -- ubuntu-bugs mailing list [email protected] https://lists.ubuntu.com/mailman/listinfo/ubuntu-bugs
