Private bug reported:
Compute Express Link (CXL) enables scalable, high-performance
interconnects for memory expansion and accelerator sharing. A key
capability in advanced deployments is the use of multi-level (cascaded)
CXL switch topologies, where multiple tiers of switches are
interconnected to form a larger fabric. This allows a significant
increase in the number of connected devices and enables flexible
resource pooling across hosts.
In a multi-level topology, upstream ports of one switch connect to
downstream ports of another, forming a hierarchy that can span multiple
layers. This architecture is essential for large-scale data center use
cases such as memory disaggregation, composable infrastructure, and
multi-tenant environments. It also introduces additional complexity in
routing, latency management, resource discovery, and fault isolation.
Within the Linux kernel, current CXL support focuses primarily on
single-level topologies and direct-attached devices. Support for multi-
level switch fabrics—including hierarchical enumeration, fabric
management, and coordinated resource allocation—is still evolving.
Enhancing OS-level support is critical to fully realize the benefits of
large-scale CXL deployments.
Feature Request:
Requested details to be enabled on OS:
Enable hierarchical enumeration of devices across multi-level CXL switch
fabrics.
Support discovery and management of cascaded switch ports and inter-switch
links.
Enhance CXL fabric management for multi-hop routing and resource allocation.
Support memory pooling and sharing across multiple switch levels and hosts.
Integrate topology-aware HDM decoder configuration across the hierarchy.
Provide latency-aware path selection and optimization mechanisms.
Enhance RAS capabilities (error propagation, containment, isolation) across
multiple switch levels.
Enable hotplug support for devices in multi-level topologies.
Provide sysfs/debugfs visibility into full fabric topology (multi-level
hierarchy).
Support virtualization and isolation in multi-tenant multi-level fabrics.
Provide tools for topology validation, visualization, and debugging.
Document supported configurations, limitations, and deployment workflows.
Business Justification:
Enables large-scale, composable infrastructure using CXL fabrics.
Improves resource utilization through shared memory and accelerators across
hosts.
Supports hyperscale and cloud data center architectures.
Enhances flexibility in deploying memory pooling and disaggregated systems.
Improves fault isolation and resilience in complex interconnect topologies.
Positions platform for future CXL 3.0+ fabric-based ecosystems.
References:
CXL 2.0 / 3.0 Specifications (Switching and Fabric Architecture)
Linux Kernel CXL Subsystem Documentation
CXL Consortium Fabric Management Specifications
Industry Whitepapers on Composable Infrastructure and Memory Pooling
** Affects: linux (Ubuntu)
Importance: Undecided
Status: New
** Information type changed from Public to Private
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https://bugs.launchpad.net/bugs/2146660
Title:
Request for CXL Multi-Level Switch Topology Support
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