Hi Carmelo, On Sat, Dec 01, 2007 at 08:52:45AM +0100, Carmelo Amoroso wrote: > Paul Mundt wrote: > >On Tue, Nov 20, 2007 at 08:30:04AM +0100, Carmelo AMOROSO wrote: > >>Same issue as SH4 (solved in the past). > > > >"Solved" is relative. What's there now works, but it's a pretty idiotic > >hack, and is certainly not solved for the multiple page size cases. The > >current implementation is certainly sub-optimal for 8kB (SH-X2 and later) > >and 64kB PAGE_SIZE (SH-4, SH-5, SH-X2 and later, etc.), and we really do > >need to take the L1 shape in to account for handling this properly. > > > >So it does work, but it will spread things out far more than they need to > >be. Most of the information needed for fixing this properly can be > >extracted from the ELF auxvt, though I never quite got around to > >finishing up the code for that. > > > do you mean passing the shm_alignment value from kernel > to ld.so through the auxvt ? if so, I could try to provide > a patch for the kernel and then update th ld.so to take care of this. > What I meant was using the same math for calculating shm_align_mask in userspace based on the L1 D-cache shape. The auxvt has pre-supported cache shape entries that we can use for populating with the cache info and support in a semi-portably fashion on the userspace side. If I recall correctly, it was Alpha that added these initially. So basically I would like to see AT_Lx_CACHESHAPE used for working this out.
The biggest issue is that we need a bit of leg-work in uClibc for parsing the auxvt in the first place. I had some code hacked together for that, but never got around to polishing it off. We need this as a base step for hooking up the vdso entry as well -- which I suspect might be of interest to you guys especially since you can do away with the context switch overhead on your sys_cacheflush ;-) _______________________________________________ uClibc mailing list [email protected] http://busybox.net/cgi-bin/mailman/listinfo/uclibc
