Sorry for typo we are using gcc-4.4.0.
Sent from my iPhone
On May 29, 2009, at 4:56 PM, Umut Tezduyar <[email protected]> wrote:
Hi Nitin,
I think both you and I are having the same problem. My question on
the thread is one before yours.
First, I don't think you can use ldrex and strex because they will
not be atomic. SWP instruction swaps register value with the value
at memory address. Swapping values with SWP instruction is atomic
and can not be interrupted.
__pthread_trylock defined in libpthread/linuxthreads/spinlock.h uses
SWP instruction.
I assume Cortex-A9 has both thumb and arm instruction set and swp is
disabled. You are kind of lucky because Cortex-M3 we are using
doesn't support arm instruction set.
Thumb2 instruction set has test and set instruction which can be
used instead of swp.
On Fri, May 29, 2009 at 1:53 PM, Nitin Garg <[email protected]>
wrote:
Hi,
We are using ARM Cortex-A9 processor. The toolchain is gcc-4.0.0 with
uClibc-0.9.30 and the kernel is 2.6.28.
Using this toolchain when we build any application like "Hello World"
and link it against pthread lib, the application does a segmentation
fault when executed on target and gives "Illegal instruction" error
message.
I debugged the problem and it came out to be that "swp" instructions
were disabled on the cortex-a9. The SWP instruction has been
deprecated starting with the ARMv6 architecture. On newer ARMv7
processors, this instruction is disabled by default but it can be
enabled by bit 10 in the System Control register. We can also build
the kernel with CONFIG_OABI_COMPAT enabled.
The real problem seems to be in the linuxthreads of uClibc where "swp"
is being used for locks.
Shall this not be replaced with ldrex/strex for ARMv7 onwards?
Regards,
Nitin
_______________________________________________
uClibc mailing list
[email protected]
http://lists.busybox.net/mailman/listinfo/uclibc
_______________________________________________
uClibc mailing list
[email protected]
http://lists.busybox.net/mailman/listinfo/uclibc
