On 14/06/10 10:28, Andrew Stubbs wrote:
Sorry, I meant to fix this, but I've been busy recently and didn't get
to it.
The makefile patch is meant to be part of the other patch I posted. I
just got my quilt set mixed up. :(
Fixed thusly. Also the memmove include you mentioned.
This patch disables SH-4 optimizations that rely on the FPU when
building for variants that don't have an FPU, such as SH-4AL.
Signed-off-by: Andrew Stubbs <[email protected]>
---
src/uclibc-mainline/libc/string/sh/sh4/memcpy.S | 2 +-
src/uclibc-mainline/libc/string/sh/sh4/memmove.c | 8 +++++++-
src/uclibc-mainline/libc/string/sh/sh4/memset.S | 2 +-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/libc/string/sh/sh4/memcpy.S b/libc/string/sh/sh4/memcpy.S
index efdaf8b..83d40d4 100644
--- a/libc/string/sh/sh4/memcpy.S
+++ b/libc/string/sh/sh4/memcpy.S
@@ -21,7 +21,7 @@
#include <sysdep.h>
#include <endian.h>
-#ifdef __LITTLE_ENDIAN__
+#if defined(__LITTLE_ENDIAN__) && defined(__FPU_ANY__)
#define MEMCPY_USES_FPU
/* Use paired single precision load or store mode for 64-bit tranfering.
* FPSCR.SZ=1,FPSCR.SZ=0 is well defined on both SH4-200 and SH4-300.
diff --git a/libc/string/sh/sh4/memmove.c b/libc/string/sh/sh4/memmove.c
index 4d52db2..67f9a1e 100644
--- a/libc/string/sh/sh4/memmove.c
+++ b/libc/string/sh/sh4/memmove.c
@@ -7,8 +7,12 @@
* Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball.
*/
-#include <string.h>
+#ifndef __FPU_ANY__
+#include "../../generic/memmove.c"
+#else
+
+#include <string.h>
#define FPSCR_SR (1 << 20)
#define STORE_FPSCR(x) __asm__ volatile("sts fpscr, %0" : "=r"(x))
@@ -115,3 +119,5 @@ void *memmove(void *dest, const void *src, size_t len)
}
libc_hidden_def(memmove)
+
+#endif
diff --git a/libc/string/sh/sh4/memset.S b/libc/string/sh/sh4/memset.S
index 1a57cb9..5cef0db 100644
--- a/libc/string/sh/sh4/memset.S
+++ b/libc/string/sh/sh4/memset.S
@@ -17,7 +17,7 @@
#include <sysdep.h>
-#ifdef __LITTLE_ENDIAN__
+#if defined(__LITTLE_ENDIAN__) && defined(__FPU_ANY__)
#define MEMSET_USES_FPU
/* Use paired single precision load or store mode for 64-bit tranfering.
* FPSCR.SZ=1,FPSCR.SZ=0 is well defined on both SH4-200 and
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