The MCF I2C-related register definitions have been renamed separately
for the MCF 528x and 532x series. This breaks the i2c-mcf driver.
I see no reason not to use common names, thus making the i2c-mcf driver
work again.
Signed-Off-By: Steve Bennett <[EMAIL PROTECTED]>
diff -urN uClinux-dist.orig/linux-2.6.x/drivers/i2c/busses/i2c-mcf.c
uClinux-dist/linux-2.6.x/drivers/i2c/busses/i2c-mcf.c
--- uClinux-dist.orig/linux-2.6.x/drivers/i2c/busses/i2c-mcf.c 2006-12-12
23:21:50.000000000 +1000
+++ uClinux-dist/linux-2.6.x/drivers/i2c/busses/i2c-mcf.c 2007-05-11
16:12:16.000000000 +1000
@@ -501,7 +501,7 @@
/* Port AS Pin Assignment Register (PASPAR) */
/* PASPA1 = 11 = AS1 pin is I2C SDA */
/* PASPA0 = 11 = AS0 pin is I2C SCL */
- *MCF_GPIO_PASPAR |= 0x000F; /* u16 declaration */
+ *MCF5282_GPIO_PASPAR |= 0x000F; /* u16 declaration */
#endif
diff -urN uClinux-dist.orig/linux-2.6.x/include/asm-m68knommu/m528xsim.h
uClinux-dist/linux-2.6.x/include/asm-m68knommu/m528xsim.h
--- uClinux-dist.orig/linux-2.6.x/include/asm-m68knommu/m528xsim.h
2007-01-25 10:44:14.000000000 +1000
+++ uClinux-dist/linux-2.6.x/include/asm-m68knommu/m528xsim.h 2007-05-11
16:12:16.000000000 +1000
@@ -63,31 +76,31 @@
*
*********************************************************************/
/* Read/Write access macros for general use */
-#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) //
Address
-#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq
Divider
-#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) //
Control
-#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
-#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data
I/O
+#define MCF_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address
+#define MCF_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq
Divider
+#define MCF_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
+#define MCF_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
+#define MCF_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
/* Bit level definitions and macros */
-#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
+#define MCF_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
-#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
+#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F))
-#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable
-#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable
-#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode
-#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode
-#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
-#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start
-
-#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit
-#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
-#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy
-#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost
-#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write
-#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt
-#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
+#define MCF_I2C_I2CR_IEN (0x80) // I2C enable
+#define MCF_I2C_I2CR_IIEN (0x40) // interrupt enable
+#define MCF_I2C_I2CR_MSTA (0x20) // master/slave mode
+#define MCF_I2C_I2CR_MTX (0x10) // transmit/receive mode
+#define MCF_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
+#define MCF_I2C_I2CR_RSTA (0x04) // repeat start
+
+#define MCF_I2C_I2SR_ICF (0x80) // data transfer bit
+#define MCF_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
+#define MCF_I2C_I2SR_IBB (0x20) // I2C bus busy
+#define MCF_I2C_I2SR_IAL (0x10) // aribitration lost
+#define MCF_I2C_I2SR_SRW (0x04) // slave read/write
+#define MCF_I2C_I2SR_IIF (0x02) // I2C interrupt
+#define MCF_I2C_I2SR_RXAK (0x01) // received acknowledge
diff -urN uClinux-dist.orig/linux-2.6.x/include/asm-m68knommu/m532xsim.h
uClinux-dist/linux-2.6.x/include/asm-m68knommu/m532xsim.h
--- uClinux-dist.orig/linux-2.6.x/include/asm-m68knommu/m532xsim.h
2006-05-26 16:18:02.000000000 +1000
+++ uClinux-dist/linux-2.6.x/include/asm-m68knommu/m532xsim.h 2007-05-11
16:12:16.000000000 +1000
@@ -131,33 +131,33 @@
*********************************************************************/
/* Read/Write access macros for general use */
-#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
-#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
-#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
-#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
-#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
+#define MCF_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address
+#define MCF_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider
+#define MCF_I2C_I2CR (volatile u8 *) (0xFC058008) // Control
+#define MCF_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status
+#define MCF_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O
/* Bit level definitions and macros */
-#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
+#define MCF_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
-#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F))
+#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F))
-#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable
-#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable
-#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode
-#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode
-#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
-#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start
-
-#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit
-#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
-#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy
-#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost
-#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write
-#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt
-#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge
+#define MCF_I2C_I2CR_IEN (0x80) // I2C enable
+#define MCF_I2C_I2CR_IIEN (0x40) // interrupt enable
+#define MCF_I2C_I2CR_MSTA (0x20) // master/slave mode
+#define MCF_I2C_I2CR_MTX (0x10) // transmit/receive mode
+#define MCF_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
+#define MCF_I2C_I2CR_RSTA (0x04) // repeat start
+
+#define MCF_I2C_I2SR_ICF (0x80) // data transfer bit
+#define MCF_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
+#define MCF_I2C_I2SR_IBB (0x20) // I2C bus busy
+#define MCF_I2C_I2SR_IAL (0x10) // aribitration lost
+#define MCF_I2C_I2SR_SRW (0x04) // slave read/write
+#define MCF_I2C_I2SR_IIF (0x02) // I2C interrupt
+#define MCF_I2C_I2SR_RXAK (0x01) // received acknowledge
-#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
+#define MCF_PAR_FECI2C (volatile u8 *) (0xFC0A4053)
/*
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