--- uClinux-dist-patch/linux-2.6.x/include/asm-m68knommu/m523xsim.h 2006-10-11 03:08:05.000000000 -0400 +++ uClinux-dist-patch-bsp/linux-2.6.x/include/asm-m68knommu/m523xsim.h 2007-07-24 14:42:37.000000000 -0400 @@ -11,6 +11,7 @@ #define m523xsim_h /****************************************************************************/ +#define MCF_REG08(x) (*(volatile unsigned char *)(x)) /* * Define the 523x SIM register set addresses. @@ -27,10 +28,37 @@ #define MCFINTC_IACKL 0x19 /* */ #define MCFINTC_ICR0 0x40 /* Base ICR register */ +/* INTC0 */ #define MCFINT_VECBASE 64 /* Vector base number */ +#define MCFINT_EPF2 2 /* Interrupt number for EPORT2 */ +#define MCFINT_EPF3 3 /* Interrupt number for EPORT3 */ +#define MCFINT_EPF4 4 /* Interrupt number for EPORT4 */ +#define MCFINT_EPF5 5 /* Interrupt number for EPORT5 */ +#define MCFINT_EPF6 6 /* Interrupt number for EPORT6 */ +#define MCFINT_EPF7 7 /* Interrupt number for EPORT7 */ #define MCFINT_UART0 13 /* Interrupt number for UART0 */ #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ +#define MCFINT_PER_INTC 64 + +/* INTC1 */ +#define MCFINT_INTC1_VECBASE (MCFINT_VECBASE+MCFINT_PER_INTC) /* Vector base number */ +#define MCFINT_TC0F 27 /* Interrupt number for eTPU Channel 0 */ +#define MCFINT_TC1F 28 /* Interrupt number for eTPU Channel 1 */ +#define MCFINT_TC2F 29 /* Interrupt number for eTPU Channel 2 */ +#define MCFINT_TC3F 30 /* Interrupt number for eTPU Channel 3 */ +#define MCFINT_TC4F 31 /* Interrupt number for eTPU Channel 4 */ +#define MCFINT_TC5F 32 /* Interrupt number for eTPU Channel 5 */ +#define MCFINT_TC6F 33 /* Interrupt number for eTPU Channel 6 */ +#define MCFINT_TC7F 34 /* Interrupt number for eTPU Channel 7 */ +#define MCFINT_TC8F 35 /* Interrupt number for eTPU Channel 8 */ +#define MCFINT_TC9F 36 /* Interrupt number for eTPU Channel 9 */ +#define MCFINT_TC10F 37 /* Interrupt number for eTPU Channel 10 */ +#define MCFINT_TC11F 38 /* Interrupt number for eTPU Channel 11 */ +#define MCFINT_TC12F 39 /* Interrupt number for eTPU Channel 12 */ +#define MCFINT_TC13F 40 /* Interrupt number for eTPU Channel 13 */ +#define MCFINT_TC14F 41 /* Interrupt number for eTPU Channel 14 */ +#define MCFINT_TC15F 42 /* Interrupt number for eTPU Channel 15 */ /* * SDRAM configuration registers. @@ -42,4 +70,122 @@ #define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ /****************************************************************************/ + +/* GPIO Registers */ + /* FEC/I2C Pin Assignment Register */ +#define MCF_GPIO_PAR_FECI2C MCF_REG08(MCF_IPSBAR + 0x100047) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) +#define MCF523x_GPIO_PAR_UART 0x100048 /* UART Pin Assignment Register */ +#define MCF523x_GPIO_PAR_QSPI 0x10004A /* QSPI Pin Assignment Register */ +#define MCF523x_GPIO_PAR_TIMER 0x10004C /* TIMER Pin Assignment Register */ +#define MCF523x_GPIO_PDDR_QSPI 0x10001A /* QSPI Pin Direction Register */ +#define MCF523x_GPIO_PDDR_TIMER 0x10001B /* TIMER Pin Direction Register */ +#define MCF523x_GPIO_PPDSDR_QSPI 0x10002A /* QSPI Pin Data Register */ +#define MCF523x_GPIO_PPDSDR_TIMER 0x10002B /* TIMER Pin Data Register */ + +/* eTPU Registers */ +#define MCF523x_ETPU 0x1D0000 /* eTPU Base */ +#define MCF523x_ETPU_CIOSR 0x00220 /* eTPU Channel Interrupt Overflow Status */ +#define MCF523x_ETPU_CIER 0x00240 /* eTPU Channel Interrupt Enable */ +#define MCF523x_ETPU_CR(c) (0x00400 + ((c)*0x10)) /* eTPU Channel c Config */ +#define MCF523x_ETPU_SCR(c) (0x00404 + ((c)*0x10)) /* eTPU Channel c Status & Ctrl */ +#define MCF523x_ETPU_SDM 0x08000 /* eTPU Shared Data Memory */ + +/* WDOG registers */ +#define MCF523x_WCR (volatile uint16_t*)(MCF_IPSBAR + 0x140000) /* control register 16 bits */ +#define MCF523x_WMR (volatile uint16_t*)(MCF_IPSBAR + 0x140002) /* modulus status 16 bits */ +#define MCF523x_MCNTR (volatile uint16_t*)(MCF_IPSBAR + 0x140004) /* count register 16 bits */ +#define MCF523x_WSR (volatile uint16_t*)(MCF_IPSBAR + 0x140006) /* service register 16 bits */ + +/* reset registers */ +#define MCF523x_RSR (volatile uint8_t*)(MCF_IPSBAR + 0x110001) /* reset reason codes */ + +/* WDOG bit level definitions and macros */ +#define MCF523x_WCR_ENABLE_BIT (0x0001) + +#define MCF523x_WCR_ENABLE (0x0001) +#define MCF523x_WCR_DISABLE (0x0000) +#define MCF523x_WCR_HALTEDSTOP (0x0002) +#define MCF523x_WCR_HALTEDRUN (0x0000) +#define MCF523x_WCR_DOZESTOP (0x0004) +#define MCF523x_WCR_DOZERUN (0x0000) +#define MCF523x_WCR_WAITSTOP (0x0008) +#define MCF523x_WCR_WAITRUN (0x0000) + +#define MCF523x_WMR_DEFAULT_VALUE (0xffff) + +/********************************************************************* +* +* Inter-IC (I2C) Module +* +*********************************************************************/ +/* Read/Write access macros for general use */ +#define MCF_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) /* Address */ +#define MCF_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) /* Freq Divider */ +#define MCF_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) /* Control */ +#define MCF_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) /* Status */ +#define MCF_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) /* Data I/O */ + +/* Bit level definitions and macros */ +#define MCF_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) + +#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)) + +#define MCF_I2C_I2CR_IEN (0x80) /* I2C enable */ +#define MCF_I2C_I2CR_IIEN (0x40) /* interrupt enable */ +#define MCF_I2C_I2CR_MSTA (0x20) /* master/slave mode */ +#define MCF_I2C_I2CR_MTX (0x10) /* transmit/receive mode */ +#define MCF_I2C_I2CR_TXAK (0x08) /* transmit acknowledge enable */ +#define MCF_I2C_I2CR_RSTA (0x04) /* repeat start */ + +#define MCF_I2C_I2SR_ICF (0x80) /* data transfer bit */ +#define MCF_I2C_I2SR_IAAS (0x40) /* I2C addressed as a slave */ +#define MCF_I2C_I2SR_IBB (0x20) /* I2C bus busy */ +#define MCF_I2C_I2SR_IAL (0x10) /* aribitration lost */ +#define MCF_I2C_I2SR_SRW (0x04) /* slave read/write */ +#define MCF_I2C_I2SR_IIF (0x02) /* I2C interrupt */ +#define MCF_I2C_I2SR_RXAK (0x01) /* received acknowledge */ + +/****************************************************************************/ + +/********************************************************************* +* +* Edge Port (EPORT) Module +* +*********************************************************************/ + +#define MCF523x_EPPAR (0x130000) +#define MCF523x_EPDDR (0x130002) +#define MCF523x_EPIER (0x130003) +#define MCF523x_EPDR (0x130004) +#define MCF523x_EPPDR (0x130005) +#define MCF523x_EPFR (0x130006) + +/********************************************************************* +* +* Chip Select (CS) Module +* +*********************************************************************/ + +#define MCF523x_CSAR0 (0x80) +#define MCF523x_CSAR3 (0xA4) +#define MCF523x_CSMR3 (0xA8) + +/********************************************************************* +* +* System Access Control Unit (SACU) +* +*********************************************************************/ + +#define MCF523x_PACR1 (0x25) +#define MCF523x_PACR2 (0x26) +#define MCF523x_PACR3 (0x27) +#define MCF523x_PACR4 (0x28) +#define MCF523x_PACR5 (0x2A) +#define MCF523x_PACR6 (0x2B) +#define MCF523x_PACR7 (0x2C) +#define MCF523x_PACR8 (0x2E) +#define MCF523x_GPACR (0x30) + #endif /* m523xsim_h */