Hi,
I'm porting uCLinux to our own design with Coldfire 5282 CPU and NAND-FLASH.
I'm using 20070130 distibution.
In 'CACHE_ENABLE' are SDRAM and (internal)FLASH defined as cacheable and all
other areas as non-cacheable.
FLASH is defined for a fixed address, but I think every design will have it on
another address.
I think this should be done with config parameters. But that is not my problem.
In the macro '__flush_cache_all' for the 5282 not in the ACR registers defined
memory areas
are defined (unlike CACHE_ENABLE) as cacheable and write-buffered.
Therefore my NAND-FLASH is cacheable with write-buffered access!
The result is, when the for-loop in 'nand_write_buf' in nand_base.c is
interrupted (timer-interrupt),
sometimes the write to the nand-port is doubled and the data in nand-flash is
corrupted.
The code in '__flush_cache_all' should be:
--- cacheflush.h.org 2007-03-22 13:15:12.000000000 +0100
+++ cacheflush.h 2007-10-25 16:12:25.000000000 +0200
@@ -52,7 +52,7 @@
#endif /* CONFIG_M5407 */
#if defined(CONFIG_M527x) || defined(CONFIG_M528x)
__asm__ __volatile__ (
- "movel #0x81400100, %%d0\n\t"
+ "movel #0x81000200, %%d0\n\t"
"movec %%d0, %%CACR\n\t"
"nop\n\t"
: : : "d0" );
A #define used in 'CACHE_ENABLE' and '__flush_cache_all' could avoid the
difference.
The second thing is that a function called 'flush_cache_all' should flush the
complete cache
and not only the instruction cache. For this 'flush_icache' is defined.
Bernd
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