Hi Greg, hi all

For memory we have problems while booting
>  uClinux/COLDFIRE(m5407)
 > COLDFIRE port done by Greg Ungerer, [EMAIL PROTECTED]
 > Coldfire was last reset by a hard reset.
 > Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne
 > On node 0 totalpages: 8192
 > zone(0): 0 pages.
 > zone(1): 8192 pages.
 > zone(2): 0 pages.
 > Kernel command line:
 > Calibrating delay loop... 118.37 BogoMIPS
 > kernel BUG at page_alloc.c:208!
 > Kernel panic: BUG!
 > In idle task - not syncing

> What we 've notice is :
> 1) all the pages are linked to the second zone (ZONE[1]) in
free_area_init_core function. i.e. page->flags > 0x10000000.
> 2) When function __free_pages_ok wants to free the page (apparently the
first to be freed) this page seems to be linked to the firts zone (ZONE[0]).
i.e. page->flags = 0 !



Apparently the page->flags is reset by something which appears to me as a
dysfunctionment of the clear_bit function located in asm-m68knommu/bitops.h
file.


here is the generated code for this function :

   int     *a = (int *) addr;
     22a0c:   2041            moveal %d1,%a0
     22a0e:   d1f9 0010 531c  addal 10531c <mem_map>,%a0
     22a14:   41e8 0018       lea %a0@(24),%a0

    int mask;
    unsigned long flags;
    a += nr >> 5;
    mask = 1 << (nr & 0x1f);
    save_flags(flags); cli();
     22a18:   40c2            movew %sr,%d2
     22a1a:   40c0            movew %sr,%d0
     22a1c:   0080 0000 0700  oril #1792,%d0
     22a22:   46c0            movew %d0,%sr

    *a &= ~mask;
     22a24:   71fc bfff       mvzw #-16385,%d0
     22a28:   c190            andl %d0,%a0@

    restore_flags(flags);
     22a2a:   46c2            movew %d2,%sr

The problem comes from the use of the MVZW instruction which clears the
highter bits of d0 register followed by an ANDL instruction.
That's why the pages are linked to zone[0] instead of zone[1].



An other similar problem appears in schedule function located in
kernel/sched.c file.

The first valuation with -1000 of c variable causes the same kind of effect.
Here is the generated code.

   25800:   75fc fc18       mvzw #-1000,%d2
   25804:   6060            bras 25866 <schedule+0x186>

  .....

   25866:   4a82            tstl %d2
   25868:   664a            bnes 258b4 <schedule+0x1d4>


Here also the problem comes from the MVZW instruction followed by and TSTL
instruction.



All this perplexs me a lot

Any ideas on that ?


Regards.
Bruno


>
> ------------------------------------------------------------------------
> Greg Ungerer  --  Chief Software Dude       EMAIL:     [EMAIL PROTECTED]
> Secure Computing Corporation                PHONE:       +61 7 3435 2888
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