The PIT code has been changed to GENERIC_CLOCKEVENTS. The priority
of the PIT timer has been decreased in favor of the DMA timer.
Signed-off-by: Benedikt Spranger <[EMAIL PROTECTED]>
Signed-off-by: Sebatian Siewior <[EMAIL PROTECTED]>
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -66,6 +66,10 @@ config TIME_LOW_RES
bool
default y
+config GENERIC_CLOCKEVENTS
+ bool
+ default n
+
config NO_IOPORT
def_bool y
@@ -112,11 +116,13 @@ config M5206e
config M520x
bool "MCF520x"
+ select GENERIC_CLOCKEVENTS
help
Freescale Coldfire 5207/5208 processor support.
config M523x
bool "MCF523x"
+ select GENERIC_CLOCKEVENTS
help
Freescale Coldfire 5230/1/2/4/5 processor support
@@ -142,6 +148,7 @@ config M5275
config M528x
bool "MCF528x"
+ select GENERIC_CLOCKEVENTS
help
Motorola ColdFire 5280/5282 processor support.
@@ -165,6 +172,7 @@ endchoice
config M527x
bool
depends on (M5271 || M5275)
+ select GENERIC_CLOCKEVENTS
default y
config COLDFIRE
@@ -675,6 +683,8 @@ config ROMKERNEL
endchoice
+source "kernel/time/Kconfig"
+
source "mm/Kconfig"
endmenu
--- a/arch/m68knommu/kernel/time.c
+++ b/arch/m68knommu/kernel/time.c
@@ -33,6 +33,7 @@ static inline int set_rtc_mmss(unsigned
return -1;
}
+#ifndef CONFIG_GENERIC_CLOCKEVENTS
/*
* timer_interrupt() needs to keep up the real-time clock,
* as well as call the "do_timer()" routine every clocktick
@@ -71,6 +72,7 @@ irqreturn_t arch_timer_interrupt(int irq
#endif
return(IRQ_HANDLED);
}
+#endif
void time_init(void)
{
--- a/arch/m68knommu/platform/coldfire/pit.c
+++ b/arch/m68knommu/platform/coldfire/pit.c
@@ -18,13 +18,15 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
-#include <linux/clocksource.h>
+#include <linux/clockchips.h>
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/coldfire.h>
#include <asm/mcfpit.h>
#include <asm/mcfsim.h>
+static DEFINE_SPINLOCK(cf_pit_lock);
+
/***************************************************************************/
/*
@@ -37,10 +39,81 @@
static u32 pit_cycles_per_jiffy;
static u32 pit_cnt;
+/*
+ * Initialize the PIT timer.
+ *
+ * This is also called after resume to bring the PIT into operation again.
+ */
+
+static void init_cf_pit_timer(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cf_pit_lock, flags);
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
+ __raw_writew(((MCF_CLK/2)/64)/HZ, TA(MCFPIT_PMR));
+ __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \
+ MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD | \
+ MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
+ break;
+
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ case CLOCK_EVT_MODE_UNUSED:
+ __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
+ break;
+
+ case CLOCK_EVT_MODE_ONESHOT:
+ /* One shot setup */
+ __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
+ __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | \
+ MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, \
+ TA(MCFPIT_PCSR));
+ break;
+
+ case CLOCK_EVT_MODE_RESUME:
+ /* Nothing to do here */
+ break;
+ }
+ spin_unlock_irqrestore(&cf_pit_lock, flags);
+}
+
+/*
+ * Program the next event in oneshot mode
+ *
+ * Delta is given in PIT ticks
+ */
+static int cf_pit_next_event(unsigned long delta,
+ struct clock_event_device *evt)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cf_pit_lock, flags);
+ __raw_writew(delta, TA(MCFPIT_PMR));
+ spin_unlock_irqrestore(&cf_pit_lock, flags);
+
+ return 0;
+}
+
+struct clock_event_device cf_pit_clockevent = {
+ .name = "coldfire_pit",
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_mode = init_cf_pit_timer,
+ .set_next_event = cf_pit_next_event,
+ .shift = 32,
+ .irq = MCFINT_VECBASE + MCFINT_PIT1,
+};
+
+
+
/***************************************************************************/
static irqreturn_t pit_tick(int irq, void *dummy)
{
+ struct clock_event_device *evt = &cf_pit_clockevent;
u16 pcsr;
/* Reset the ColdFire timer */
@@ -48,7 +121,10 @@ static irqreturn_t pit_tick(int irq, voi
__raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
pit_cnt += pit_cycles_per_jiffy;
- return arch_timer_interrupt(irq, dummy);
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+
}
/***************************************************************************/
@@ -79,7 +155,7 @@ static cycle_t pit_read_clk(void)
static struct clocksource pit_clk = {
.name = "pit",
- .rating = 250,
+ .rating = 100,
.read = pit_read_clk,
.shift = 20,
.mask = CLOCKSOURCE_MASK(32),
@@ -88,10 +164,47 @@ static struct clocksource pit_clk = {
/***************************************************************************/
+/*
+ * Since the PIT overflows every tick, its not very useful
+ * to just read by itself. So use jiffies to emulate a free
+ * running counter:
+ */
+static cycle_t cf_pit_get_cycles(void)
+{
+ volatile unsigned long *ipr;
+ unsigned long pcntr;
+ u32 jifs;
+ static int old_count;
+ static u32 old_jifs;
+
+ jifs = jiffies;
+
+ ipr = (volatile unsigned long *)
+ (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR);
+
+ pcntr = __raw_readw(TA(MCFPIT_PCNTR));
+ if (pcntr > old_count && jifs == old_jifs)
+ pcntr = old_count;
+
+ old_count = pcntr;
+ old_jifs = jifs;
+
+ return (cycle_t)(jifs*((MCF_CLK/2)/64)/HZ) + pcntr;
+}
+
void hw_timer_init(void)
{
u32 imr;
+ cf_pit_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
+ cf_pit_clockevent.mult = div_sc(((MCF_CLK/2)/64),
+ NSEC_PER_SEC, 32);
+ cf_pit_clockevent.max_delta_ns =
+ clockevent_delta2ns(0xFFFF, &cf_pit_clockevent);
+ cf_pit_clockevent.min_delta_ns =
+ clockevent_delta2ns(0xF, &cf_pit_clockevent);
+ clockevents_register_device(&cf_pit_clockevent);
+
setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
__raw_writeb(ICR_INTRCONF, INTC0 + MCFINTC_ICR0 + MCFINT_PIT1);
@@ -99,13 +212,6 @@ void hw_timer_init(void)
imr &= ~MCFPIT_IMR_IBIT;
__raw_writel(imr, INTC0 + MCFPIT_IMR);
- /* Set up PIT timer 1 as poll clock */
- pit_cycles_per_jiffy = FREQ / HZ;
- __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
- __raw_writew(pit_cycles_per_jiffy, TA(MCFPIT_PMR));
- __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW |
- MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
-
pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift);
clocksource_register(&pit_clk);
}
--
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