Hi Thomas,
Thomas Chou wrote:
Change the instruction to flush data cache to "flushda".
NiosII instruction spec: "flushda" flushes the cache line only if the
addressed memory location is currently cached. By contrast, the "flushd"
instruction flushes the cache line even if the addressed memory location
is not cached.
The flush range for cache_invalidate_lines() is limited to the cache
size, so that the time spent can be reduced.
Signed-off-by: Thomas Chou <[EMAIL PROTECTED]>
Applied to uClinux-dist, thanks.
Regards
Greg
linux-2.6.x/arch/nios2nommu/mm/memory.c | 33 ++++++++++++++++---------------
1 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/linux-2.6.x/arch/nios2nommu/mm/memory.c
b/linux-2.6.x/arch/nios2nommu/mm/memory.c
index b2ffdf1..4e089d5 100644
--- a/linux-2.6.x/arch/nios2nommu/mm/memory.c
+++ b/linux-2.6.x/arch/nios2nommu/mm/memory.c
@@ -44,18 +44,6 @@
#include <asm/io.h>
/*
- * cache_clear() semantics: Clear any cache entries for the area in question,
- * without writing back dirty entries first. This is useful if the data will
- * be overwritten anyway, e.g. by DMA to memory. The range is defined by a
- * _physical_ address.
- */
-
-void cache_clear (unsigned long paddr, int len)
-{
-}
-
-
-/*
* Define cache invalidate functions. The instruction and data cache
* will need to be flushed. Write back the dirty data cache and invalidate
* the instruction cache for the range.
@@ -88,7 +76,7 @@ static __inline__ void cache_invalidate_data(unsigned long
paddr, int len)
__asm__ __volatile__ (
"1:\n\t"
- "flushd 0(%0)\n\t"
+ "flushda 0(%0)\n\t"
"add %0,%0,%2\n\t"
"blt %0,%1,1b\n\t"
: : "r" (sset),"r" (eset), "r" (nasys_dcache_line_size));
@@ -98,9 +86,11 @@ static __inline__ void cache_invalidate_data(unsigned long
paddr, int len)
static __inline__ void cache_invalidate_lines(unsigned long paddr, int len)
{
unsigned long sset, eset;
+ int dlen = min(len, nasys_dcache_size);
+ int ilen = min(len, nasys_icache_size);
sset = (paddr & (nasys_dcache_size - 1)) & (~(nasys_dcache_line_size - 1));
- eset = (((paddr & (nasys_dcache_size - 1)) + len) &
(~(nasys_dcache_line_size - 1))) + nasys_dcache_line_size;
+ eset = (((paddr & (nasys_dcache_size - 1)) + dlen) &
(~(nasys_dcache_line_size - 1))) + nasys_dcache_line_size;
__asm__ __volatile__ (
"1:\n\t"
@@ -110,7 +100,7 @@ static __inline__ void cache_invalidate_lines(unsigned long
paddr, int len)
: : "r" (sset),"r" (eset), "r" (nasys_dcache_line_size));
sset = (paddr & (nasys_icache_size - 1)) & (~(nasys_icache_line_size - 1));
- eset = (((paddr & (nasys_icache_size - 1)) + len) &
(~(nasys_icache_line_size - 1))) + nasys_icache_line_size;
+ eset = (((paddr & (nasys_icache_size - 1)) + ilen) &
(~(nasys_icache_line_size - 1))) + nasys_icache_line_size;
__asm__ __volatile__ (
"1:\n\t"
@@ -134,7 +124,6 @@ void cache_push (unsigned long paddr, int len)
cache_invalidate_lines(paddr, len);
}
-
/*
* cache_push_v() semantics: Write back any dirty cache data in the given
* area, and invalidate those entries at least in the instruction cache. This
@@ -171,6 +160,18 @@ void cache_push_all (void)
}
/*
+ * cache_clear() semantics: Clear any cache entries for the area in question,
+ * without writing back dirty entries first. This is useful if the data will
+ * be overwritten anyway, e.g. by DMA to memory. The range is defined by a
+ * _physical_ address.
+ */
+
+void cache_clear (unsigned long paddr, int len)
+{
+ cache_invalidate_data(paddr, len);
+}
+
+/*
* dcache_push() semantics: Write back and dirty data cache and invalidate
* the range.
*/
--
------------------------------------------------------------------------
Greg Ungerer -- Chief Software Dude EMAIL: [EMAIL PROTECTED]
Secure Computing Corporation PHONE: +61 7 3435 2888
825 Stanley St, FAX: +61 7 3891 3630
Woolloongabba, QLD, 4102, Australia WEB: http://www.SnapGear.com
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