Hi Michael,
Michael Schnell wrote:
The problem turned out to be incorrect cache flushing on the signal
trampoline (arch/kernel/signal.c -- setup_frame()).
Why should the cache need to be flushed ? Is the due to the silly "MMU
after Cache" hardware glitch of the ARM architecture ?
The original code (and how it is still done in m68k, maybe other
arches too) put code _in_ the stack to deal with the signal
return cleanup. That will hit the data cache, and depending on cache
type some time sooner or later RAM. But the code cache could
be now be stale relative to those addresses.
Regards
Greg
------------------------------------------------------------------------
Greg Ungerer -- Chief Software Dude EMAIL: [EMAIL PROTECTED]
SnapGear -- a Secure Computing Company PHONE: +61 7 3435 2888
825 Stanley St, FAX: +61 7 3891 3630
Woolloongabba, QLD, 4102, Australia WEB: http://www.SnapGear.com
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