Michael Schnell wrote:
> In my understanding to implement FUTEX, the arch either needs to provide
> an appropriate monolithic memory operation (e.g. "load and inc" or "test
> and set"), or needs to be non-SMP and allow for disable/enable
> interrupts directly in user-space. (The second option seems to hold for
> most non-MMU-systems.)
(The common name is "atomic" not "monolithic" :-)
For non-SMP systems without useful atomic ops, the best option might
be what ARM does. There's a routine __kernel_cmpxchg ("atomic compare
and exchange") at a fixed address in memory. All other atomic ops must
call that routine.
The kernel scheduler checks the instruction pointer on every interrupt
and kernel entry. If the instruction pointer is inside
__kernel_cmpxchg, after the load and before the store, the interrupt
adjusts it to make __kernel_cmpxchg start again.
That makes it atomic without disabling interrupts. (Which I don't
think you can do on ARM no-MMU in userspace anyway).
You could copy that method for your architecture, if you don't want to
add atomic instructions to your FPGA :-)
However, since you have an FPGA, load-locked/store-conditional atomic
sequences are probably easy instructions to add _if_ you have only one
CPU. You'd just implement a store-guard flag which is cleared
whenever an interrupt or trap occurs - trivial :-)
-- Jamie
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