Jivin Thomas Häberle lays it down ...
>
> First of all: Thanks for the quick, frequent, interesting and informative
> response!!
>
> The numbers mentioned by the developer were a gut feeling and rough
> estimation, not derived by tests and measurements,
> but because I had neither I also had no basis to disagree.
>
> The CPUs in use are PowerPCs (MPC852 & MPC8247) from the PowerQuicc II family
> with 8MB to 32MB of RAM,
> thus AFAIK the cache design is "descent" and the cache has not to be flushed
> completly on a context switch, right?
>
> I'll take your information into account, propose some tests and let you know
> if we get proper results!
I think it might have been posted in one of the threads, but just in
case it wasn't, here is a doc that gives numbers to MMU vs. no MMU.
http://opensrc.sec.samsung.com/document.html
Always good to have some real numbers ;-)
Cheers,
Davidm
--
David McCullough, david_mccullo...@securecomputing.com, Ph:+61 734352815
McAfee - SnapGear http://www.snapgear.com http://www.uCdot.org
_______________________________________________
uClinux-dev mailing list
uClinux-dev@uclinux.org
http://mailman.uclinux.org/mailman/listinfo/uclinux-dev
This message was resent by uclinux-dev@uclinux.org
To unsubscribe see:
http://mailman.uclinux.org/mailman/options/uclinux-dev
