By the way, why would a 16650 have a fifo size of 1? That would give really awful performance. 16550's have fifo sizes of 16. I thought 16650's were at least that and usually bigger.
Sorry, Lennart, wrong copy-paste. Actually my settings are: [PORT_16550A] = { .name = "16550A", .fifo_size = 16, .tx_loadsz = 16, .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, .flags = UART_CAP_FIFO, -- Agava Design Bureau 620026, Russia, 620026, Yekaterinburg, Bazhova str. 174 tel./fax. +7 (343) 262-92-76, 262-92-78, 262-92-87 http://kb-agava.ru _______________________________________________ uClinux-dev mailing list uClinux-dev@uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev@uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev