I see, you are trying to figure out access rights, not set up the eTPU.
Well, if there are all really 0, then that means only supervisor mode
can r/w them. Not sure why you would need execute privilege from an
I/O register, so that could be right.


On Thu, Dec 9, 2010 at 8:24 AM, Sébastien MENNETRIER
<smennetr...@epsi.fr> wrote:
> I am reading 0x40000030 to see the value of GPACR.
> In the file "arch/m68knommu/platform/523x/config.c", GPACR is defined :
>         uint8_t *gpacr = (uint8_t *) (MCF_IPSBAR + MCF523x_GPACR);
>         *gpacr = 0x0C;
> And "MCF523x_GPACR" is defined in file "arch/m68k/include/asm/m523xsim.h" :
> #define MCF523x_GPACR (0x30)
>
> In the file "arch/m68k/include/asm/colfire.h", I see :
> #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
> || \
>     defined(CONFIG_M520x)
> #undef MCF_MBAR
> #define MCF_MBAR MCF_IPSBAR
> And MCF523x_ETPU is define :
> #define MCF523x_ETPU 0x1D0000
> So I think that "MCF_MBAR + MCF523x_ETPU" = "IPSBAR + 0x1D0000" =
> 0x401D0000.
> And the structure is defined at this adresse.
>
> 2010/12/9 Jim Donelson <ucli...@jimdonelson.com>
>>
>> Well, I'm not sure why you are reading 0x40000030, when the registers
>> start at 0x401D0000.
>> "MCF_MBAR + MCF523x_ETPU sounds wrong as the registers are defined to
>> start at IPSBAR + 0x1D0000, so 0x401D0000 sound correct to me for the
>> first register.
>>
>>
>> On Thu, Dec 9, 2010 at 7:03 AM, Sébastien MENNETRIER
>> <smennetr...@epsi.fr> wrote:
>> > Hello,
>> > Thanks for your help Jim.
>> > The structure seem have the good alignement.
>> > The structure is declaring at the adress : 0x401D0000
>> >       struct eTPU_struct *eTPU = (struct eTPU_struct *)0x401D0000;
>> > And in the kernel code :
>> > In file "./arch/m68k/include/asm/m523xsim.h" : #define MCF523x_ETPU
>> >  0x1D0000
>> > In the driver file "./drivers/misc/mcfetpu_serial.c", there are
>> > "MCF_MBAR +
>> > MCF523x_ETPU" with MCF_MBAR = MCF_IPSBAR = 0x40000000
>> > So it's the same adress.
>> > I made a driver to see the GPACR and the PACR* :
>> > uint8_t *gpacr = (uint8_t *) (0x40000030);
>> > uint8_t *pacr0 = (uint8_t *) (0x40000024);
>> > uint8_t *pacr1 = (uint8_t *) (0x40000025);
>> > uint8_t *pacr2 = (uint8_t *) (0x40000026);
>> > uint8_t *pacr3 = (uint8_t *) (0x40000027);
>> > uint8_t *pacr4 = (uint8_t *) (0x40000028);
>> > uint8_t *pacr5 = (uint8_t *) (0x4000002A);
>> > uint8_t *pacr6 = (uint8_t *) (0x4000002B);
>> > uint8_t *pacr7 = (uint8_t *) (0x4000002C);
>> > uint8_t *pacr8 = (uint8_t *) (0x4000002E);
>> > printk(KERN_DEBUG "GPACR : %#x", *gpacr);
>> > printk(KERN_DEBUG "PACR0 : %#x", *pacr0);
>> > printk(KERN_DEBUG "PACR1 : %#x", *pacr1);
>> > printk(KERN_DEBUG "PACR2 : %#x", *pacr2);
>> > printk(KERN_DEBUG "PACR3 : %#x", *pacr3);
>> > printk(KERN_DEBUG "PACR4 : %#x", *pacr4);
>> > printk(KERN_DEBUG "PACR5 : %#x", *pacr5);
>> > printk(KERN_DEBUG "PACR6 : %#x", *pacr6);
>> > printk(KERN_DEBUG "PACR7 : %#x", *pacr7);
>> > printk(KERN_DEBUG "PACR8 : %#x", *pacr8);
>> > But they are all equal at "0x00".
>> > It's very strange, isn't it?
>> > Are they an other security to protect the register?
>> > MENNETRIER Sébastien
>> > FRANCE
>> >
>> >
>> > 2010/12/9 Jim Donelson <ucli...@jimdonelson.com>
>> >>
>> >> Probably has to do with structure alignment. Not sure what the packing
>> >> options/pragmas are for that situation.
>> >>
>> >> On Thu, Dec 9, 2010 at 4:54 AM, Sébastien MENNETRIER
>> >> <smennetr...@epsi.fr>
>> >> wrote:
>> >>>
>> >>> Hello,
>> >>> I work on a MCF5235 coldfire and with "uClinux-dist-20101026". I try
>> >>> to
>> >>> use the eTPU.
>> >>> I have install the driver and dowload the application to use eTPU on
>> >>> freescale website.
>> >>> When I start the programme, there are an error : "Access Error
>> >>> Exception
>> >>> 12: Error on data read".
>> >>> So I modify the file :
>> >>> "uClinux-dist/linux-2.6.x/arch/m68knommu/platform/523x/config.c".
>> >>> I have modify "*gpacr" and all "*pacrx" to obtain the access to the
>> >>> register.
>> >>> uint8_t *gpacr = (uint8_t *) (MCF_IPSBAR + MCF523x_GPACR);
>> >>> uint8_t *pacr1 = (uint8_t *) (MCF_IPSBAR + MCF523x_PACR1);
>> >>> uint8_t *pacr4 = (uint8_t *) (MCF_IPSBAR + MCF523x_PACR4);
>> >>> uint8_t *pacr7 = (uint8_t *) (MCF_IPSBAR + MCF523x_PACR7);
>> >>> uint8_t *pacr8 = (uint8_t *) (MCF_IPSBAR + MCF523x_PACR8);
>> >>>
>> >>>
>> >>> //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
>> >>> // *gpacr = 0x04;
>> >>> // *pacr1 = 0x40; /* EIM required for Chip Select access */
>> >>> // *pacr4 = 0x40; /* I2C */
>> >>> // *pacr7 = 0x44; /* INTC0 & 1 handy for debug */
>> >>> // *pacr8 = 0x40; /* FEC MAC */
>> >>>
>> >>>
>> >>> //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
>> >>>                 *gpacr = 0x0C;
>> >>> *pacr1 = 0x44; /* EIM required for Chip Select access */
>> >>> *pacr4 = 0x44; /* I2C */
>> >>> *pacr7 = 0x44; /* INTC0 & 1 handy for debug */
>> >>> *pacr8 = 0x44; /* FEC MAC */
>> >>>
>> >>> But  this change did not solve the problem.
>> >>> Can you help me please?
>> >>>
>> >>> MENNETRIER Sébastien
>> >>> FRANCE
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