JohnSwenson wrote: 
> 
> 
> The parameters I am actually interested in do not use huge amounts of
> processing power so it should be good on the wandboard.
> 
> Thanks,
> 
> John S.

And earlier you  said.

JohnSwenson wrote: 
> I have done extensive testing of different DAC chips and digital filters
> and have come to the conclusion that one of the biggest problem with
> almost all DAC chips these days is the digital filter. Every one of them
> (including the ESS) use a complex digital filter rather than something
> like a true SINC, attempting to get better numbers in the spec sheet
> without spending the required silicon resourses normally required to get
> those numbers with a simple filter. My testing has shown that these
> complex filters are quite audible and one of the biggest detriments to
> really good sound out there. Using a DAC chip without a digital filter
> and implementing one in an FPGA using a straight forward basic filter
> design sounds much better than using the filters in the chips
> themselves.

Is your objection to having filters design using interpolated FIR
methods like the response I pasted below? Would this be considered
"complex" per your post above? Are you planning to use a filter that is
just a truncated (possibly windowed) SINC function instead? I'm just
trying to understand what you consider "simple" and "complex"
considering that what may be a mathematically -simple- approach may
require more computationally -complex- implementation to achieve
reasonable rejection.


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