On Sun, May 23, 2010 at 2:42 AM, Mike Frysinger <vap...@gentoo.org> wrote: >> Yes, the memory is parallel and it is connected with data/addres >> interface to the bluecore4 chip, but the chip itself does not support >> JTAG. > > right, but the address lines of the chip have to go somewhere. if they go to > the part which you connect to via JTAG, and that part allows for wiggling of > its lines via JTAG, you can talk to the chip. this is how we do it on Blackfn > boards: > [parallel flash (CFI]) <-- data/addr --> [Blackfin CPU] <-- JTAG --> [USB > FT2232H] <-- Linux development system --> [urjtag] > > urjtag wiggles the Blackfin's data/addr lines that are connected to the > parallel flash chip
Mike I understand how JTAG access works :-) In this case this is different - end user access to the CFI Parallel Flash is provided by the IC with its own SPI interface ( [Flash]--<CFI>--[IC]--<SPI>--o ), as there is no JTAG support, probably to simplify the IC design. SPI implementation would be similar (even simpler) than JTAG on the cable that can already do some JTAG bitbang. This is why I was wondering if SPI was already implemented in UrJTAG. It could also help me solve some issues with Serial SPI Flash onboard a Xilinx FPGA board (where direct SPI access to the memory is available on a separate connector), and possibly others in future using an elegant all-in-one-box manner... so the next step is to implement the code! :-) Best regards :-) Tomek -- CeDeROM, SQ7MHZ, http://www.tomek.cedro.info ------------------------------------------------------------------------------ _______________________________________________ UrJTAG-development mailing list UrJTAG-development@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/urjtag-development
