Hi,
there is a bug in the intel.c flash program routine.
After you write CFI_INTEL_CMD_WRITE_TO_BUFFER, you are just polling the
SR_READY in the status register. But according the the datasheet [1] p.24, you
have to reissue the CMD_WRITE_TO_BUFFER command to let the status register
update its SR_READY bit.
Attached is a patch.
[1] http://www.numonyx.com/Documents/Datasheets/319942_J3-65nm_256-
Mbit_MLC%20DS.pdf
--
wkr Michael
diff --git a/urjtag/src/flash/intel.c b/urjtag/src/flash/intel.c
index 2bd9f4a..d5811dd 100644
--- a/urjtag/src/flash/intel.c
+++ b/urjtag/src/flash/intel.c
@@ -341,9 +341,10 @@ intel_flash_program_buffer (urj_flash_cfi_array_t *cfi_array,
/* issue command WRITE_TO_BUFFER */
URJ_BUS_WRITE (bus, cfi_array->address,
CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
- URJ_BUS_WRITE (bus, adr, CFI_INTEL_CMD_WRITE_TO_BUFFER);
/* poll XSR7 == 1 */
- while (!((sr = URJ_BUS_READ (bus, cfi_array->address) & 0xFE) & CFI_INTEL_SR_READY)); /* TODO: add timeout */
+ do {
+ URJ_BUS_WRITE (bus, adr, CFI_INTEL_CMD_WRITE_TO_BUFFER);
+ } while (!((sr = URJ_BUS_READ (bus, cfi_array->address) & 0xFE) & CFI_INTEL_SR_READY)); /* TODO: add timeout */
/* write count value (number of upcoming writes - 1) */
URJ_BUS_WRITE (bus, adr, wcount - 1);
------------------------------------------------------------------------------
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