Hello, I get this error when playing an SVF to a Xilinx XC9572XL (stepping 1). I'm using urJTAG v10 on Windows with a FT2232 programmer.
jtag> detect IR length: 8 Chain length: 1 Device Id: 01011001011000000100000010010011 (0x0000000059604093) Filename: c:\bsdl/xc9572xl_vq44_1532.bsd jtag> svf c:\svf\xc95test.svf stop Error svf: mismatch at position 17 for TDO in input file between line 40 col 1 and line 40 col 49 Error occurred for SVF command SDR. jtag> Here are lines 36 through 40 of the SVF file: // Loading devices with 'fbulk' instruction. SIR 8 TDI (ed) ; SDR 18 TDI (03ffff) SMASK (03ffff) ; RUNTEST 200000 TCK; SDR 18 TDI (03fffd) TDO (000001) MASK (000003) ; Stepping 1 isn't directly supported by the default urJtag libraries, so I specified the path to a Xilinx BSDL file that seemed to work. When I exported the SVF Impact warned me that there were commands that might not be supported by all cables. I'm not sure if this is related. I also made and tested a CoolRunner-II version of the project. urJTAG had no problem programming the same project synthesized for a XC2C64A (into an XC2C64A). The only other SVF player handy was actually a microcontroller-based *X*SVF player (from XAPP058 app note). It programmed the XSVF version fine, so I can verify that the chip is OK. I found a discussion in the urJTAG mailing list archive about using this CPLD/stepping and it working, so I assume it's my problem. Does anyone have any suggestions? Thank you, Ian ------------------------------------------------------------------------------ The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb _______________________________________________ UrJTAG-development mailing list UrJTAG-development@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/urjtag-development
